| Distance: | Resume alert | Resumes 21 - 30 of 6087 |
Software Engineer
Morganville, NJ
... I & II, Multivariable Calculus, Differential Equations, Electronic Devices Skills Computer Languages: Python, C, C++, Matlab, Verilog, Java, NodeJs Platform Skills: Windows Server, Ubuntu, Linux Work Experience & Projects Github: https://github.com ... - Jun 12
... I & II, Multivariable Calculus, Differential Equations, Electronic Devices Skills Computer Languages: Python, C, C++, Matlab, Verilog, Java, NodeJs Platform Skills: Windows Server, Ubuntu, Linux Work Experience & Projects Github: https://github.com ... - Jun 12
Project Manager Electrical Systems
Peabody, MA
... SKILLS Programming: C C++ MATLAB Python VHDL Verilog Perl Unix. Embedded Systems: Raspberry Pi Arduino I2C UART SPI. Software: AutoCAD SolidWorks Xilinx Vivado OrCAD Altium PSpice CST Visio SAP Revit. Miscellaneous: Soldering (THT & SMT) Cathode Ray ... - Jun 11
... SKILLS Programming: C C++ MATLAB Python VHDL Verilog Perl Unix. Embedded Systems: Raspberry Pi Arduino I2C UART SPI. Software: AutoCAD SolidWorks Xilinx Vivado OrCAD Altium PSpice CST Visio SAP Revit. Miscellaneous: Soldering (THT & SMT) Cathode Ray ... - Jun 11
Computer Engineering Entry Level
Plano, TX, 75024
... SPI module to render images onto VGA Skills ● Intermediate knowledge of Digital Design Concepts ● Intermediate skills in Verilog and C ● Experience with Altera FPGAs ● Intermediate Knowledge of Quartus ● Basic knowledge of ModelSim and SignalTap ... - Jun 11
... SPI module to render images onto VGA Skills ● Intermediate knowledge of Digital Design Concepts ● Intermediate skills in Verilog and C ● Experience with Altera FPGAs ● Intermediate Knowledge of Quartus ● Basic knowledge of ModelSim and SignalTap ... - Jun 11
Design Engineer Hardware
Dublin, CA
... MIPS Pipelined Processor with RAW hazard Resolution ASIC Physical Design, OpenLane Designed & Verified 5-stage 32-bitpipelined MIPS processor using Verilog HDL in Xilinx Vivado 2024.2. Implemented instruction-level parallelism & Integrated ... - Jun 11
... MIPS Pipelined Processor with RAW hazard Resolution ASIC Physical Design, OpenLane Designed & Verified 5-stage 32-bitpipelined MIPS processor using Verilog HDL in Xilinx Vivado 2024.2. Implemented instruction-level parallelism & Integrated ... - Jun 11
Systems Engineer Computer Engineering
San Diego, CA
... Familiar with Verilog, C, C++, Python, and Java. Experienced in full-stack web development using React and Django, with skills in circuit design, signal processing, and microcontroller programming. Strong problem-solving abilities, attention to ... - Jun 11
... Familiar with Verilog, C, C++, Python, and Java. Experienced in full-stack web development using React and Django, with skills in circuit design, signal processing, and microcontroller programming. Strong problem-solving abilities, attention to ... - Jun 11
Fpga Engineer Hands-On
Sacramento, CA
PRAPTI SHAH 279-***-**** **************@*****.*** linkedin.com/in/prapti-shah-71489b19a Sacramento – CA PROFESSIONAL SUMMARY Versatile FPGA Engineer with 1.5 years of hands-on experience in FPGA development, specializing in Verilog HDL, RTL ... - Jun 10
PRAPTI SHAH 279-***-**** **************@*****.*** linkedin.com/in/prapti-shah-71489b19a Sacramento – CA PROFESSIONAL SUMMARY Versatile FPGA Engineer with 1.5 years of hands-on experience in FPGA development, specializing in Verilog HDL, RTL ... - Jun 10
Computer Engineering Azure Data
Rockwall, TX, 75087
... ● Office/VSS Tools: Microsoft Word, Microsoft Office, Excel, PowerPoint, Outlook, GitHub ● Hardware: TinkerCad, Arduino, PSpice, Verilog, Matlab ● Certifications: DP 900 – Microsoft Azure Data Fundamental Certified, OSHA certified WORK EXPERIENCE ... - Jun 10
... ● Office/VSS Tools: Microsoft Word, Microsoft Office, Excel, PowerPoint, Outlook, GitHub ● Hardware: TinkerCad, Arduino, PSpice, Verilog, Matlab ● Certifications: DP 900 – Microsoft Azure Data Fundamental Certified, OSHA certified WORK EXPERIENCE ... - Jun 10
Design Engineer Rtl
Hyderabad, Telangana, India
... Technical Skills Programming Languages: Verilog,VHDL, System Verilog Tools: Xilinx Vivado, Modelsim, Chipscope, MATLAB, Synopsys VCS Protocols: AHB, APB, UART, SPI, I2C, Ethernet, GTX Transceivers, SERDES High-Speed Interfaces: DDRx, ADC, DAC, USB, ... - Jun 10
... Technical Skills Programming Languages: Verilog,VHDL, System Verilog Tools: Xilinx Vivado, Modelsim, Chipscope, MATLAB, Synopsys VCS Protocols: AHB, APB, UART, SPI, I2C, Ethernet, GTX Transceivers, SERDES High-Speed Interfaces: DDRx, ADC, DAC, USB, ... - Jun 10
Electrical Engineering Hands-On
Edmonds, WA
... accepted on ICIP 2025 Skills & Abilities · Languages & Scripting: C, C++, Python, Matlab, Bash · HDL & Hardware Design: Verilog, SystemVerilog, SystemC, RTL Design, CDC, FSM, Computer Architecture (Pipelineing, Risc-V, Cache, ISA design) · Tools: ... - Jun 06
... accepted on ICIP 2025 Skills & Abilities · Languages & Scripting: C, C++, Python, Matlab, Bash · HDL & Hardware Design: Verilog, SystemVerilog, SystemC, RTL Design, CDC, FSM, Computer Architecture (Pipelineing, Risc-V, Cache, ISA design) · Tools: ... - Jun 06
Project Management C++
Brookside, DE, 19713
... Soochow University Suzhou, Jiangsu, China Master Program of Computer Engineering, Computer Applications July 1997 - December 1999 Concentrations: C/C++, VHDL/Verilog Relevant Coursework: Networking, Database, OS, Assembly and C in MCU, Graphic by C ... - Jun 05
... Soochow University Suzhou, Jiangsu, China Master Program of Computer Engineering, Computer Applications July 1997 - December 1999 Concentrations: C/C++, VHDL/Verilog Relevant Coursework: Networking, Database, OS, Assembly and C in MCU, Graphic by C ... - Jun 05