| Distance: | Resume alert | Resumes 21 - 30 of 5855 |
VLSI & Embedded Systems Engineer
Bengaluru, Karnataka, India
SRUJAN N M +91-963******* ***************@*****.*** Professional Summary VLSI and Embedded Systems Engineer with knowledge of Verilog, VHDL, SystemVerilog, CMOS design, FPGA implementation, Embedded C, ARM-based development, RTOS, hardware- software ... - Sep 26
SRUJAN N M +91-963******* ***************@*****.*** Professional Summary VLSI and Embedded Systems Engineer with knowledge of Verilog, VHDL, SystemVerilog, CMOS design, FPGA implementation, Embedded C, ARM-based development, RTOS, hardware- software ... - Sep 26
ASIC SoC Design Verification Engineer
Richardson, TX
... TECHNICAL SKILLS • Languages: Verilog, SystemVerilog, UVM, Perl, C/C++, Python, Java, MIPS. • Verification Methodologies: Testbench Architecture Development, Constraint-Random Verification, Assertion-Based Verification (ABV), Functional and Code ... - Sep 24
... TECHNICAL SKILLS • Languages: Verilog, SystemVerilog, UVM, Perl, C/C++, Python, Java, MIPS. • Verification Methodologies: Testbench Architecture Development, Constraint-Random Verification, Assertion-Based Verification (ABV), Functional and Code ... - Sep 24
UCIe ASIC Protocol Verification Engineer
Phoenixville, PA
... FPGA-Assisted Validation and Emulation Workflow Verilog, SystemVerilog, Python, Xilinx ISE, Linux • Mapped synthesizable RTL modules into an FPGA-based prototype environment to validate functional behavior beyond RTL simulation and strengthen pre ... - Sep 24
... FPGA-Assisted Validation and Emulation Workflow Verilog, SystemVerilog, Python, Xilinx ISE, Linux • Mapped synthesizable RTL modules into an FPGA-based prototype environment to validate functional behavior beyond RTL simulation and strengthen pre ... - Sep 24
Senior Product Development & ATE Engineering Leader
Pune, Maharashtra, India
... Technology Well versed with MIL-Std-704D, MIL-Std-461C, MIL-Std-810D and DO160G certification standards Software Skills Verilog, VHDL, SystemC Xilinx ISE(12.0), ModelSim(v6.1), NC_SystemC(2.0), Cadence_ldv (v 3.2), Synopsis DC PSPICE, ORCAD (v9.0) ... - Sep 23
... Technology Well versed with MIL-Std-704D, MIL-Std-461C, MIL-Std-810D and DO160G certification standards Software Skills Verilog, VHDL, SystemC Xilinx ISE(12.0), ModelSim(v6.1), NC_SystemC(2.0), Cadence_ldv (v 3.2), Synopsis DC PSPICE, ORCAD (v9.0) ... - Sep 23
Design Verification Engineer
Houston, TX
... Strong knowledge of SystemVerilog, Verilog, VHDL, C, C++, Python, Perl, Tcl, and Shell scripting. Experienced in developing UVM-based testbenches, constrained random verification (CRV), & functional verification. Hands-on experience with ... - Sep 19
... Strong knowledge of SystemVerilog, Verilog, VHDL, C, C++, Python, Perl, Tcl, and Shell scripting. Experienced in developing UVM-based testbenches, constrained random verification (CRV), & functional verification. Hands-on experience with ... - Sep 19
ASIC Engineer
United States
... Processors, Integrated Circuit Design, Digital Electronics, Machine Learning, Data Structures TECHNICAL SKILLS Languages: Verilog, C, C++, SystemVerilog, Python, TCL, MATLAB, VHDL, SQL, C#, Ruby, Bash, Perl, R Tools: Questa Sim, ModelSim, Synopsys ... - Sep 19
... Processors, Integrated Circuit Design, Digital Electronics, Machine Learning, Data Structures TECHNICAL SKILLS Languages: Verilog, C, C++, SystemVerilog, Python, TCL, MATLAB, VHDL, SQL, C#, Ruby, Bash, Perl, R Tools: Questa Sim, ModelSim, Synopsys ... - Sep 19
Design Verification Engineer (UVM, SV, Python)
Fort Collins, CO
... GPA: 3.62/4.0 Jamia Hamdard Delhi, India Jul 2017 – Jun 2021 TECHNICAL SKILLS HDL (Hardware Description Languages): Verilog, SystemVerilog Programming Languages: Python, C/C++ Protocols: AMBA AXI, AMBA AHB, APB, I2C, SPI, UART, USART EDA Tools ... - Sep 17
... GPA: 3.62/4.0 Jamia Hamdard Delhi, India Jul 2017 – Jun 2021 TECHNICAL SKILLS HDL (Hardware Description Languages): Verilog, SystemVerilog Programming Languages: Python, C/C++ Protocols: AMBA AXI, AMBA AHB, APB, I2C, SPI, UART, USART EDA Tools ... - Sep 17
RTL Verification Engineer (UVM/SystemVerilog)
Grapevine, TX
... • Tools: Cadence Virtuoso, Spectre, Xilinx Vivado, ModelSim, ADS, Synopsys-VCS, Verdi, XA, Primesim, Primewave • Programming: Verilog, VHDL, SystemVerilog, UVM, UVM-RAL, Verilog-A/MS • Analog Skills: Analog MOS transistor models, Current mirrors, ... - Sep 16
... • Tools: Cadence Virtuoso, Spectre, Xilinx Vivado, ModelSim, ADS, Synopsys-VCS, Verdi, XA, Primesim, Primewave • Programming: Verilog, VHDL, SystemVerilog, UVM, UVM-RAL, Verilog-A/MS • Analog Skills: Analog MOS transistor models, Current mirrors, ... - Sep 16
RTL Design & Verification Engineer
Aurora, CO, 80014
... Strong in SystemVerilog, Verilog, RTL design, microarchitecture, UVM, SVA, constrained-random testing, coverage-driven verification, and simulation debug, with experience across block, subsystem, and SoC-level verification. Proficient with Synopsys ... - Sep 15
... Strong in SystemVerilog, Verilog, RTL design, microarchitecture, UVM, SVA, constrained-random testing, coverage-driven verification, and simulation debug, with experience across block, subsystem, and SoC-level verification. Proficient with Synopsys ... - Sep 15
SoC/UVM Design Verification Engineer
Bareilly, Uttar Pradesh, India
... TECHNICAL SKILLS Languages and HDL: SystemVerilog, Verilog, Python Verification Methodology: UVM, Constrained-Random Verification (CRV), Directed Testing, UVM RAL, Scoreboards & Reference Models, SystemVerilog Assertions (SVA), Functional Coverage, ... - Sep 10
... TECHNICAL SKILLS Languages and HDL: SystemVerilog, Verilog, Python Verification Methodology: UVM, Constrained-Random Verification (CRV), Directed Testing, UVM RAL, Scoreboards & Reference Models, SystemVerilog Assertions (SVA), Functional Coverage, ... - Sep 10