| Distance: | Resume alert | Resumes 21 - 30 of 5898 |
SOFTWARE ENGINEER IV
United States
... SYSTEMS DESIGN ENGINEER MediaTek, India APRIL 2008 — AUGUST 2009 Developed CODA, an IDE for chipset designers to automate file generation (e.g., RTL Verilog, XML, C/C++ headers), enhancing productivity and consistency. Designed META CLI, a console ... - Feb 26
... SYSTEMS DESIGN ENGINEER MediaTek, India APRIL 2008 — AUGUST 2009 Developed CODA, an IDE for chipset designers to automate file generation (e.g., RTL Verilog, XML, C/C++ headers), enhancing productivity and consistency. Designed META CLI, a console ... - Feb 26
Electrical Engineer & Computer Engineer Student Leader
Bayonne, NJ
... hosted by IEEE-APS, IEEE North Jersey, and IEEE Photonics FPGA-Based CPU August 2024 - Nov 2024 a 32-bit CPU in VHDL and Verilog using Xilinx Vivado Analog Multiplexing System Printed Circuit Board August 2024 - Sept 2024 Designed a signal ... - Feb 25
... hosted by IEEE-APS, IEEE North Jersey, and IEEE Photonics FPGA-Based CPU August 2024 - Nov 2024 a 32-bit CPU in VHDL and Verilog using Xilinx Vivado Analog Multiplexing System Printed Circuit Board August 2024 - Sept 2024 Designed a signal ... - Feb 25
Electromagnetic Design & Motor Control Engineer
Chennai, Tamil Nadu, India
... Designed and implemented a PI controller on a DSP+FPGA board using Embedded C and Verilog to maintain constant output voltage regardless of load and input voltage variations. The Proposed model reduces the current rating of active devices and ... - Feb 25
... Designed and implemented a PI controller on a DSP+FPGA board using Embedded C and Verilog to maintain constant output voltage regardless of load and input voltage variations. The Proposed model reduces the current rating of active devices and ... - Feb 25
Data Analyst: SQL & BI Enthusiast with QA Flair
Atlanta, GA
... •Characterized 0.18u and 90nm standard cell libraries, custom IO cells using layout simulation flow at Best/Worst/nominal case corners as well as other corners using Adopt and performed QA on the generated Synopsys, Verilog behavioral models as ... - Feb 20
... •Characterized 0.18u and 90nm standard cell libraries, custom IO cells using layout simulation flow at Best/Worst/nominal case corners as well as other corners using Adopt and performed QA on the generated Synopsys, Verilog behavioral models as ... - Feb 20
ASIC/RTL design engineer
Hyderabad, Telangana, India
... KEY SKILLS - Programming Languages: C Verilog System Verilog. - EDA: RTL Simulation Synthesis and analysis(Synopsys Design Compiler, Fusion Compiler) - Scripting: TCL, Perl. - Core VLSI knowledge: RTL design, digital architecture, IP based design ... - Feb 15
... KEY SKILLS - Programming Languages: C Verilog System Verilog. - EDA: RTL Simulation Synthesis and analysis(Synopsys Design Compiler, Fusion Compiler) - Scripting: TCL, Perl. - Core VLSI knowledge: RTL design, digital architecture, IP based design ... - Feb 15
Electrical Design Engineer with Controls & HW Expertise
California City, CA
... mitigation, thermal management, ESD protection, board bring-up • Semiconductor & VLSI – Hardware Design & Verification: Verilog HDL, SystemVerilog, UVM, OVM, C, Python, FPGA programming, ASIC development, VLSI design, static timing analysis, mixed ... - Feb 12
... mitigation, thermal management, ESD protection, board bring-up • Semiconductor & VLSI – Hardware Design & Verification: Verilog HDL, SystemVerilog, UVM, OVM, C, Python, FPGA programming, ASIC development, VLSI design, static timing analysis, mixed ... - Feb 12
Senior IT Project & Field Operations Manager
Timisoara, Timis, Romania
... of California, San Diego – Extension English for Business Communication HDL Programming Fundamentals Design using VHDL and Verilog Radio Frequency Circuit Design Fundamentals of Analog IC Design Embedded Controller Programming I Video Compression: ... - Feb 12
... of California, San Diego – Extension English for Business Communication HDL Programming Fundamentals Design using VHDL and Verilog Radio Frequency Circuit Design Fundamentals of Analog IC Design Embedded Controller Programming I Video Compression: ... - Feb 12
Embedded Systems Engineer - Real-Time & FPGA Specialist
United States
... Proficient in Embedded C, MATLAB/Simulink, VHDL/Verilog, with strong expertise in RTOS, hardware–software integration, and control system design. Skilled in applying ISO 26262 safety standards, MIL/SIL/HIL testing, and static code analysis to ... - Feb 12
... Proficient in Embedded C, MATLAB/Simulink, VHDL/Verilog, with strong expertise in RTOS, hardware–software integration, and control system design. Skilled in applying ISO 26262 safety standards, MIL/SIL/HIL testing, and static code analysis to ... - Feb 12
Aspiring CS & Data Science Professional
Williamsburg, VA
... Plugin/Snippet Dev RESTful APIs, JSON Back-end: Java, JS (Node), PHP, Python, C++, Flask (Python) Engineering Tools: Verilog, MATLAB, MATLAB App Designer, draw.io (Flowcharts), MySQL (ERDs), Arduino IDE Databases & Data Storage: MySQL, NoSQL ... - Jan 30
... Plugin/Snippet Dev RESTful APIs, JSON Back-end: Java, JS (Node), PHP, Python, C++, Flask (Python) Engineering Tools: Verilog, MATLAB, MATLAB App Designer, draw.io (Flowcharts), MySQL (ERDs), Arduino IDE Databases & Data Storage: MySQL, NoSQL ... - Jan 30
Embedded Firmware Engineer IoT, HW/SW Co-Design
Houston, TX
... microchip and Keil Uvision 5 and Digital System Design and Testability Labs(FPGA-5CEBA4FC23) in Verilog, SystemVerilog using Quartus Prime and also assisted with debugging and testing Systems, monitored their progress, and enforced lab safety rules. ... - Jan 29
... microchip and Keil Uvision 5 and Digital System Design and Testability Labs(FPGA-5CEBA4FC23) in Verilog, SystemVerilog using Quartus Prime and also assisted with debugging and testing Systems, monitored their progress, and enforced lab safety rules. ... - Jan 29