RTL Design & Verification Engineer

Gnana Praseeda Goudi

RTL DESIGN & VERIFICATION ENGINEER

+1-720-***-**** *****.*@**********.*** LinkedIn Open to Relocate SUMMARY

RTL Design & Verification Engineer with 3+ years of experience developing, integrating, and verifying digital logic across ASIC, SoC, and semiconductor programs. Strong in SystemVerilog, Verilog, RTL design, microarchitecture, UVM, SVA, constrained-random testing, coverage-driven verification, and simulation debug, with experience across block, subsystem, and SoC-level verification. Proficient with Synopsys VCS, Verdi, Design Compiler, SpyGlass, Questa, Python, Tcl, and Linux, covering AMBA AXI/APB interfaces, CDC/RDC, UVM RAL, formal verification, gate-level simulation, X-propagation, power-aware verification, synthesis, timing analysis, and coverage closure. TECHNICAL SKILLS

RTL Design: SystemVerilog, Verilog, Synthesizable RTL, Microarchitecture, FSMs, Datapaths, Control Logic, Parameterized RTL, Clock & Reset Design

CPU / Microarchitecture: RISC-V ISA (RV32I), CPU/Microprocessor Architecture, Datapath & Control Path, Pipelining, Interrupts & Exceptions, Memory-Mapped I/O, AXI/APB Interfaces

Verification: UVM, SVA, Coverage-Driven Verification, Constrained-Random Testing, Functional & Code Coverage, Assertion & Toggle Coverage, UVM RAL, Regression, Coverage Closure, Scoreboards, Monitors, Drivers, Sequences Protocols: AMBA, AXI, AXI4-Lite, APB, AHB, AXI-Stream, SPI, I2C, UART EDA & Analysis: VCS, Verdi, Design Compiler, SpyGlass, Xcelium, Questa/ModelSim, Vivado, RTL Lint, CDC/RDC, Synthesis, STA, Gate-Level Simulation, X-Propagation, Power-Aware Verification, Formal Verification Automation: Python, Tcl, Shell, Linux, Regression Automation, Log Analysis, Git, GitHub Engineering: Verification Planning, Test Strategy, Design Reviews, Code Reviews, Jira, Confluence, Defect Tracking EXPERIENCE

RTL Design & Verification Engineer AMD, USA Jan 2026 – Present

• Developed synthesizable SystemVerilog RTL from specifications and microarchitecture requirements for 5G modem and SoC datapath blocks, implementing FSMs, counters, control logic, and configurable interfaces across 12+ reusable IP modules.

• Defined verification scenarios and built UVM environments for AXI and APB interfaces, using UVM RAL, sequences, monitors, scoreboards, assertions, and constrained-random stimulus to exercise 1,800+ functional cases across normal and error conditions.

• Refined datapath RTL through Design Compiler synthesis and timing analysis, addressing critical paths, logic structure, and pipeline behavior to deliver a 0.42 ns timing improvement across selected design blocks.

• Root-caused 60+ RTL, protocol, reset, and X-propagation issues through VCS simulation, Verdi waveform analysis, and targeted assertions, tracing transaction behavior across block and subsystem boundaries before integration.

• Automated simulation, regression triage, coverage reporting, and gate-level verification flows with Python and Tcl, removing approximately 15 hours of manual effort per major verification and release cycle.

• Supported SoC integration and verification planning through design reviews, Git-based development, Jira defect tracking, and power- aware verification activities, contributing to 5 major integration milestones across RTL and verification teams. Digital Design & Verification Engineer HCL Tech, INDIA Mar 2022 – Jul 2024

• Developed RTL and verification strategies for block and subsystem-level ASIC/SoC programs, applying SystemVerilog, UVM, and coverage-driven verification to reduce simulation compute requirements by 18% across 3 environments.

• Engineered synthesizable Verilog and SystemVerilog RTL for 18 ASIC/SoC modules, translating microarchitecture requirements into FSMs, datapaths, control logic, and reset sequencing across 4 subsystem releases.

• Automated regression execution, coverage analysis, and failure triage with Python and Tcl, increasing nightly throughput from 280 to 410 tests and accelerating feedback across RTL and verification cycles.

• Root-caused 75+ RTL, protocol, CDC, reset, and functional defects using VCS, Verdi, assertions, and waveform analysis, reducing average debug turnaround from 6 hours to 4 hours across active regressions.

• Closed 160+ functional, code, assertion, and toggle coverage gaps through constrained-random testing, directed scenarios, UVM RAL checks, and SystemVerilog Assertions, strengthening coverage closure across 3 environments.

• Validated RTL across 20+ clock and reset domains using SpyGlass lint, CDC/RDC analysis, formal checks, and X-propagation analysis, identifying 90+ violations before synthesis and integration handoff.

• Optimized 7 RTL blocks through Design Compiler synthesis, static timing analysis, area analysis, and gate-level simulation, identifying design changes that saved approximately 22 engineering hours across 6 release cycles.

• Streamlined verification closure through test planning, verification documentation, Git-based code reviews, Jira triage, and Confluence tracking, contributing to resolution of 120+ design and verification issues across semiconductor programs. PROJECTS

AMBA-Based SoC Peripheral Subsystem Verification SystemVerilog, Verilog, UVM, SVA, AXI4-Lite, APB, Synopsys VCS, Verdi, Python

• Designed an AMBA-based peripheral subsystem as a master's coursework project, implementing 7 RTL modules for register control, timers, interrupts, and AXI4-Lite/APB communication using SystemVerilog and Verilog.

• Developed a SystemVerilog/UVM verification environment with UVM RAL, sequences, drivers, monitors, scoreboards, constrained- random testing, and 25+ SVA assertions, executing 600+ simulations and achieving 92% functional coverage. 32-bit RISC-V Processor Core (RV32I) SystemVerilog, Verilog, RISC-V RV32I ISA, CPU Microarchitecture, Datapath & Control Path, Pipelining, Interrupts & Exceptions, Memory-Mapped I/O, AXI/APB Interfaces

• Designed and implemented a 32-bit RISC-V processor core based on the RV32I ISA, developing synthesizable SystemVerilog RTL for the datapath, control path, instruction decode, ALU, register file, pipelining, and memory-mapped I/O.

• Developed and verified interrupt/exception handling and AXI/APB interfaces using SystemVerilog, assertions, directed and constrained-random testing, simulation, and waveform analysis to validate instruction execution and processor-level functionality. Asynchronous FIFO Design & Verification SystemVerilog, Verilog, UVM, SVA, Questa, ModelSim, Python, Tcl, Git, Linux

• Designed a parameterized asynchronous FIFO for a master's digital design project, implementing dual-clock read/write logic, Gray- code pointer synchronization, full/empty detection, and configurable data depth using SystemVerilog.

• Developed a SystemVerilog/UVM verification environment with 18 SVA assertions, formal checks, and coverage analysis, executing 2,000+ transactions and achieving 94% functional coverage across CDC, reset, overflow/underflow, and boundary conditions. EDUCATION

Master of Science in Electrical Engineering, Specialization: VLSI Design and Micro-electronics University of Colorado Denver, Denver, CO

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