ASIC SoC Design Verification Engineer

Harish Sekar

**********@*****.*** 469-***-****

SUMMARY

Design Verification Engineer with 5+ years of experience in ASIC/SoC functional verification and Verification IP (VIP) development. Strong expertise in SystemVerilog and UVM, with a track record of architecting scalable testbenches for compute subsystems, DDR/LPDDR memory interfaces, and AXI/AHB/APB protocols. Leverages advanced methodologies—including ABV/SVA, formal/property checking, and CDC/RDC analysis—to expose deep logic bugs and ensure control-path correctness. Hands-on experience with DFT/JTAG validation, FPGA proof-of-concepts, and building Python/Perl-based regression automation across VCS, Xcelium, Questa, and JasperGold environments to accelerate verification closure.

TECHNICAL SKILLS

• Languages: Verilog, SystemVerilog, UVM, Perl, C/C++, Python, Java, MIPS.

• Verification Methodologies: Testbench Architecture Development, Constraint-Random Verification, Assertion-Based Verification

(ABV), Functional and Code Coverage, System-Level Testing, Protocol Compliance.

• Design Verification Frameworks: UVM, OVM, Formal Verification (JasperGold), Emulation (Zebu, Palladium).

• Tools: ModelSim/QuestaSim, Synopsys VCS and Verdi, Cadence Incisive/Xcelium, Xilinx Vivado, Synopsys Design Compiler, DVE, SpyGlass.

• Architecture Knowledge: SoC Architecture, CPU and GPU Architecture, Cache Coherency, AXI, AHB, APB Protocols, Memory Subsystem, and Hierarchical Verification.

• Scripting and Automation: Python, Shell Scripting, TCL, and Perl for regression setup, data analysis, and environment automation. WORK EXPERIENCE

AMD August 2025 – Present.

Design Verification Engineer Austin, TX.

• Executed verification of compute-centric SoC subsystems using SystemVerilog/UVM, with focus on multi core CPU integration, protocol compliance, and subsystem interaction across shared control and data paths.

• Verified DDR/LPDDR and PHY-related control flows covering initialization sequencing, training control, calibration programming, and timing configuration behavior. Developed reusable UVM-based verification architecture for block- and subsystem-level validation.

• Applied formal/property checking for control logic, connectivity, and protocol corner cases to improve bug detection efficiency.

• Drove ABV/SVA-based verification for protocol timing, handshake correctness, reset sequencing, and control-path behavior.

• Supported DFT and ATPG validation through verification of scan enable logic, test-mode transitions, and JTAG-accessible control behavior in collaboration with diagnostics teams.

• Performed CDC/RDC analysis to identify unsafe asynchronous interactions, synchronization gaps, and reset-domain issues across multi-clock subsystem integrations.

• Automated regressions, test configuration, and failure triage using Python, Perl, Tcl, and Shell, improving verification debug efficiency. SIEMENS July 2019 – June 2023.

ASIC Verification Engineer Mumbai, India.

• Developed and validated reusable SystemVerilog/UVM Verification IP (VIP) components for AMBA protocols, ensuring robust protocol compliance and control-path verification for customer ASIC integrations.

• Implemented coverage-driven verification (CDV) strategies, utilizing cross-coverage models, verification plans, and data-driven analytics to identify stimulus gaps and accelerate coverage closure for complex protocol VIPs.

• Stressed AXI, AHB, and APB VIP interfaces across complex burst traffic, arbitration, and back-to-back transaction scenarios to validate protocol checkers and constrained-random stimulus generation.

• Built FPGA-based proof-of-concept environments (Xilinx Zynq-7000 / Vivado) to validate image processing IP, utilizing hardware-assisted verification methodologies to accelerate subsystem testing.

• Implemented ABV using SVA for protocol timing, reset behavior, and handshake validation, improving corner-case logic bugs.

• Architected reusable UVM drivers, monitors, and scoreboards, aligning with methodology frameworks to support scalable deployment across varied customer integration environments.

• Executed CDC/RDC methodologies (utilizing Questa) on multi-clock reference designs to analyze metastability risks

• Validated JTAG and boundary-scan network behavior for ensuring correct test-mode transitions and supporting DFT methodologies.

• Automated regressions, log parsing, and result reporting using Python, improving EDA tool evaluation cycles. EDUCATION

Master of Science in Computer Engineering. August 2023-May 2025. University of Texas at Dallas.

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