Design Verification Engineer (UVM, SV, Python)

Fardeen Wasey

385-***-**** *************@*****.*** LinkedIn: in/fardeenwasey YouTube: @fardeenwasey PROFESSIONAL SUMMARY

Design Verification Engineer with 2.6 years of experience and Technical Educator with over 100 UVM/SV lectures. Specializes in UVM environments utilizing Formal Verification and leveraging Front-end EDA tools for comprehensive verification. EXPERIENCE

Design Verification Engineer

Relic Solutions LLC, Elmont, NY Feb 2026 – Present

• Deployed scalable SystemVerilog/UVM verification environments across 3 distinct client ASIC IPs.

• Authored 50+ constrained-random stimulus models and layered virtual sequences to validate microarchitectural features.

• Optimized regression pipelines by triaging nightly 100+ failures via deep waveform analysis, reducing debug time by 30%. ASIC Design Verification Engineer

Eliyan Corporation, Santa Clara, CA Feb 2025 – Jan 2026

• Developed SystemVerilog/UVM testbenches and components to verify complex transactions and interconnect logic.

• Deployed Formal verification with 120+ SVAs to mathematically prove critical state machines and catch corner-case violations.

• Automated simulation workflows by independently developing Python scripts to parse over 1,000+ lines of simulation logs daily, streamlining the regression pipeline and saving 10+ hours per week in manual triage. Design Verification Engineer

Broadcom, India Aug 2021 – Jul 2022

• Integrated reusable UVM components into established legacy environments, executing block-level test plans for SoC subsystem.

• Closed 100% of functional coverage gaps by analyzing complex waveform data to debug protocol violations.

• Managed daily regression, utilizing custom shell scripts to accelerate the isolation and reporting of critical RTL defects by 20%. EDUCATION

Master of Science, Electrical and Computer Engineering GPA: 3.63/4.0 Portland State University Portland, OR Sep 2022 – Dec 2024 Relevant Coursework: Pre-Silicon Validation, Formal Verification, Advanced Computer Architecture, ASIC: Modeling and Synthesis, Post-Silicon Validation, Python Scripting, Microprocessor System Design, Digital IC Design, Engineering and Technology Management Bachelor of Technology, Electronics and Communication Engineering GPA: 3.62/4.0 Jamia Hamdard Delhi, India Jul 2017 – Jun 2021

TECHNICAL SKILLS

HDL (Hardware Description Languages): Verilog, SystemVerilog Programming Languages: Python, C/C++

Protocols: AMBA AXI, AMBA AHB, APB, I2C, SPI, UART, USART EDA Tools: Siemens QuestaSim, ModelSim, Synopsys VC Formal, VCS, Cadence Virtuoso, JasperGold, AMD Vivado Key Concepts: Object Oriented Programming (OOP), Universal Verification Methodology (UVM), Assertion Based Verification (ABV), RTL Design, Constrained Random Verification, Functional Coverage, Code Coverage, CPU, Microarchitecture, DDR, Cache, Pipelining, GPU, Branch Prediction, Out of order execution, RISC-V ISA, x86 Assembly Language, DPI-C, Regression, Debugging, Git PROJECTS

RTL Design and Verification of an I2C-based Memory Subsystem

• Implemented a synthesizable I2C memory subsystem featuring a master interface (50 MHz system clock / 100 kHz I2C clock) and a slave controller supporting clock stretching.

• Built a scalable UVM testbench with 15+ virtual sequences and 50+ test cases; applied 20+ concurrent SVAs. RTL Design and Verification of Asynchronous FIFO Buffer

• Designed a parameterized 512x8 Asynchronous FIFO with gray code pointers, drafting the HLDS and achieving >95% functional and 100% code coverage using constraint randomization and cross-coverage bins.

• Achieved over >95% functional and 100% code coverage by defining complex covergroups with cross-coverage bins. Formal Verification & Sequential Equivalence Check of Digital Designs

• Performed Sequential Equivalence Check (SEC) between a sequential design with its modified/optimized variant to check for unwanted changes in the functionality and utilized TCL script for automation of the process.

• Analyzed FSM designs using AEP, FXP, FCA, & FPV with SV Assertions to detect and rectify false properties.

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