Design Verification Engineer

NIKESH REDDY KUNREDDY

Design Verification Engineer

Email: ***************@*****.*** Ph no: +1-281-***-**** PROFESSIONAL SUMMARY

Over 3+ years of experience in Design Verification, ASIC/SoC Verification, RTL Verification, and Firmware Engineering.

Strong knowledge of SystemVerilog, Verilog, VHDL, C, C++, Python, Perl, Tcl, and Shell scripting.

Experienced in developing UVM-based testbenches, constrained random verification (CRV), & functional verification.

Hands-on experience with SystemVerilog Assertions (SVA), functional coverage, code coverage, and coverage closure.

Good understanding of RTL verification, IP verification, SoC verification, CDC, RDC, FSM, pipeline, and low-power

(UPF) verification.

Experienced in verifying AXI4, AHB, APB, PCIe, USB, Ethernet, I2C, SPI, UART, MIPI, and DDR4/DDR5 protocols.

Proficient with Synopsys VCS, Cadence Xcelium, Siemens QuestaSim, Verdi, DVE, SpyGlass, JasperGold, and VC Formal for simulation, debugging, linting, and formal verification.

Skilled in Python, Perl, Tcl, and Shell scripting for regression automation, log parsing, and verification workflow automation using Git, SVN, Jenkins, and Gerrit.

Familiar with Linux, UNIX, Agile Scrum, JIRA, Bugzilla, Confluence, ASIC, FPGA, ARM, RISC-V, AMBA architecture, cache coherency, DMA, and embedded systems.

Excellent communication, problem-solving, analytical, teamwork, adaptability, and interpersonal skills with a strong passion for learning new technologies and delivering high-quality verification solutions. TECHNICAL SKILLS

Programming Languages: SystemVerilog, Verilog, VHDL, C, C++, Python, Perl, Tcl, Shell Scripting

Verification Methodologies: UVM, OVM, VMM, UVM RAL, Constrained Random Verification (CRV), Assertion-Based Verification (ABV), Functional Verification

Verification & RTL: ASIC Verification, SoC Verification, IP Verification, RTL Verification, Testbench Development, Functional Coverage, Code Coverage, Coverage Closure

Protocols: AXI3, AXI4, AXI-Lite, AHB, APB, PCIe, USB, Ethernet, I2C, SPI, UART, MIPI, DDR4, DDR5

RTL Concepts: FSM, Pipeline Verification, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Low Power Verification (UPF), AMBA Architecture

EDA & Debug Tools: Synopsys VCS, Verdi, DVE, SpyGlass, PrimeTime, Cadence Xcelium, JasperGold, QuestaSim, ModelSim, SimVision

Formal Verification: JasperGold, VC Formal, Formal Property Verification (FPV), Equivalence Checking, Static Analysis

Firmware & Automation: Embedded C, Firmware Development, Python Automation, Perl, Tcl, Shell Scripting, Regression Automation, Log Parsing

Version Control & Tools: Git, GitHub, GitLab, SVN, Jenkins, Gerrit, JIRA, Bugzilla, Confluence, Agile Scrum

Operating Systems & Hardware: Linux, UNIX, Windows, FPGA, Embedded Systems, ARM, RISC-V, Multi-Core SoC, DMA, Interrupts, Cache Coherency

PROFESSIONAL WORK EXPERIENCE

Honeywell Technologies Houston, TX Design Verification Engineer Jan 2026 – Present Responsibilities:

Spearheaded the development of comprehensive Verification Plans (VPlan) by evaluating architecture & microarchitecture specifications, defining verification scope, functional coverage goals, test strategies, & sign-off criteria for complex ASIC & SoC designs.

Architected scalable UVM verification environments for subsystem-level integration, enabling reusable verification infrastructure across multiple IP blocks and reducing duplicate verification effort.

Verified SoC subsystems such as AXI interconnects, DMA engines, interrupt controllers, memory controllers, cache interfaces, clock modules, and peripherals under different conditions.

Designed advanced constrained-random scenarios, virtual sequences, layered stimulus generation, and protocol- aware scoreboards to validate corner-case functionality and improve design robustness.

Implemented assertion-driven verification using SystemVerilog Assertions and formal property checking to identify protocol violations, deadlocks, reset sequencing issues, and data integrity failures early in verification.

Improved regression stability by 35% through optimization of reusable verification components, automated failure triage, and enhanced regression management using Python, Tcl, and Jenkins.

Performed low-power verification using UPF, validating power domains, isolation cells, retention logic, power state transitions, and reset recovery to ensure power-aware functional correctness.

Executed CDC/RDC analysis using SpyGlass and Questa CDC, eliminating critical clock synchronization issues and improving RTL quality before simulation sign-off.

Drove coverage closure activities by analyzing functional, assertion, and code coverage reports, identifying verification gaps, and developing targeted tests that increased verification completeness above 98% before tape-out.

Performed root-cause analysis of simulation failures using Verdi and DVE waveform debugging while collaborating closely with RTL designers to resolve functional discrepancies and improve design quality.

Participated in design reviews, verification reviews, bug triage meetings, and architecture discussions to ensure alignment between verification strategy, RTL implementation, and project milestones.

Supported end-to-end verification sign-off, including planning, testbench design, simulation, debugging, formal verification, coverage closure, regression analysis, and tape-out readiness in Agile environments. Environment: SystemVerilog, UVM, SVA, Verilog, Synopsys VCS, Verdi, DVE, SpyGlass, JasperGold, Questa CDC, AXI4, AXI- Lite, AHB, APB, DMA, Interrupt Controller, Cache Coherency, Memory Controller, UPF, CDC, RDC, Python, Tcl, Shell Scripting, Git, Jenkins, Linux, JIRA, Confluence, ASIC Verification, SoC Verification, Functional Verification, Coverage Closure, Regression Automation, Formal Verification. Intuitive Machines Houston, TX Firmware Verification Engineer Feb 2025 – Dec 2025 Responsibilities:

Executed firmware verification and validation for embedded aerospace solutions, developing structured test plans to ensure functional accuracy and compliance with system-level specifications.

Verified firmware interaction with hardware peripherals including SPI, UART, I2C, GPIO, DMA, and interrupt controllers using C/C++ and SystemVerilog-based validation environments.

Designed automated validation scripts using Python and Shell scripting to streamline firmware regression testing, reducing manual validation effort by 30%.

Performed register-level validation, memory-mapped I/O testing, and boot sequence verification for embedded processor-based platforms.

Executed simulation and debugging using Cadence Xcelium, SimVision, and ModelSim to identify firmware and hardware integration issues.

Collaborated with hardware and RTL teams to debug interface-level defects, improving firmware stability and reducing issue resolution time by 25%.

Maintained automated regression suites and analyzed test results using Git, JIRA, and Confluence.

Validated communication interfaces including PCIe, Ethernet, USB, SPI, and UART, ensuring reliable data transfer between firmware and hardware modules.

Participated in Agile sprint planning, code reviews, and defect tracking to support timely firmware releases.

Supported firmware integration, system bring-up, and verification activities on Linux-based embedded platforms throughout the product development lifecycle.

Environment: Embedded C, C++, Python, SystemVerilog, Cadence Xcelium, SimVision, ModelSim, PCIe, Ethernet, USB, SPI, UART, I2C, DMA, Linux, Git, JIRA, Confluence, Firmware Verification, Embedded Systems. Synopsys Inc. Hyderabad, India Design Verification Engineer Jan 2023 – Jul 2024 Responsibilities:

Developed UVM-based verification environments using SystemVerilog for ASIC and IP-level functional verification.

Created reusable UVM components, constrained random test cases, & directed tests to validate complex RTL designs.

Verified AXI4, AHB, and APB protocols by developing protocol-specific sequences, monitors, and scoreboards.

Executed simulations using Synopsys VCS and debugged RTL issues with Verdi, DVE, and waveform analysis.

Created SystemVerilog Assertions (SVA) and functional coverage for effective ASIC and SoC verification.

Automated regression execution and log analysis using Python and Tcl, improving regression efficiency by 20%.

Performed SpyGlass Lint, JasperGold, and code coverage analysis to identify RTL issues & ensure design compliance.

Collaborated with RTL, design, and verification teams to resolve functional bugs, achieve 95%+ functional coverage, and support successful verification sign-off.

Environment: SystemVerilog, Verilog, UVM, SVA, Synopsys VCS, Verdi, DVE, SpyGlass, JasperGold, AXI4, AHB, APB, Python, Tcl, Git, Linux, ASIC Verification, SoC Verification, IP Verification, RTL Verification, Functional Coverage, Code Coverage, Regression Testing.

EDUCATION

Master of Science in Electrical Engineering (MSEE) from University of Houston, TX, USA.

Bachelor of Technology in Electronics and Communication Engineering (ECE) from Sreenidhi Institute of Science and Technology, Hyderabad, India

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