ASIC Engineer

Disha Athani

*******@****.*** 919-***-**** Raleigh, NC linkedin.com/in/disha-athani *************@*****.*** EDUCATION

North Carolina State University, Master of Science in Computer Engineering Aug 2024 – May 2026 Raleigh, NC GPA: 3.5/4

Relevant Coursework: ASIC and FPGA Design, ASIC Verification, Advanced Computer Architecture, Microprocessor Architecture, Digital Signal Processing, Electronic System Level and Physical Design, Neural Networks, Computer Networks

Cummins College of Engineering, B. Tech in Electronics and Telecommunication Aug 2018 – Jun 2022 Pune, India GPA: 8.45/10

Relevant Coursework: VLSI, Advanced Processors, Integrated Circuit Design, Digital Electronics, Machine Learning, Data Structures

TECHNICAL SKILLS

Languages: Verilog, C, C++, SystemVerilog, Python, TCL, MATLAB, VHDL, SQL, C#, Ruby, Bash, Perl, R Tools: Questa Sim, ModelSim, Synopsys Design Compiler, Cadence Virtuoso, Xilinx Vivado, Keil μVision, Linux, Unix, Github

Concepts: RTL design, ASIC Design flow, Logic Synthesis, Timing Analysis, Finite State Machine (FSM), RISC-V, UVM, CPU Architecture, DFT, SoC, Design Verification, I2C/SPI/UART, RFIC Design, GPU, Coverage Analysis, ML, AI, IoT ACADEMIC PROJECTS

Functional Verification of LC3 Microcontroller of Decode Stage, UVM Feb 2026 – Mar 2026

•Developed a UVM testbench to verify the Decode stage of the LC3 microcontroller.

•Generated 50 randomized transactions and validated DUT outputs using a scoreboard that compared actual results against predictions from predictor.

•Achieved 100% functional coverage by debugging mismatches to root cause. Dynamic Instruction Scheduling Simulator, C++ Oct 2025 – Nov 2025

•Constructed a 9 stage out-of-order superscalar processor with dynamic instruction scheduling, supporting configurable issue queue and reorder buffer sizes to emulate real-world microarchitectural behavior.

•Analyzed pipeline performance under data and structural hazards, using IPC and cycle counts over 50K+ instructions. RTL Implementation of Transformer-Based Self-Attention Model, Verilog Jan 2025 – Mar 2025

•Designed a Verilog hardware module for scaled dot-product attention, computing Q, K, V matrices, score matrix (S), and output (Z) using an FSM and SRAM-based memory management for efficient data flow.

•Optimized the design to cut clock cycles, achieving a 94% speed improvement. Branch Predictor, C++ Nov 2024 – Nov 2024

•Simulated bimodal, gshare, and hybrid prediction techniques as part of a Microarchitecture course to analyze branch prediction accuracy and performance.

Cache Simulator, C++, Microprocessor Architecture Sep 2024 – Oct 2024

•Built a configurable L1/L2 cache hierarchy simulator (WBWA) with LRU replacement and stream-buffer prefetching to analyze memory hierarchy behavior, validated using SPEC benchmark traces.

•Tuned prefetching and cache policies to reduce L2 miss rates and lower total memory traffic across the evaluated SPEC workloads.

WORK EXPERIENCE

Chipchop Pte. Ltd., FPGA Engineer Jul 2026 – Present Remote

•Contributed to FPGA design, coding, and verification tasks for AI-assisted testing workflows, supporting validation of 3+ FPGA design modules in collaboration with the AI team.

•Documented test results, observations, and improvement suggestions across design review cycles.

•Participated in design reviews and technical discussions with senior engineers, gaining hands-on exposure to industry best practices.

PwC, Associate Engineer Aug 2022 – Apr 2024 Pune, India

•Streamlined 12 approval workflows, reducing manual intervention and enhancing processing efficiency by 40% through effective risk management and systematic debugging.

•Collaborated with 6+ cross-functional stakeholders to align requirements across parallel teams.

•Engineered SQL queries to validate payroll data consistency, improving error detection by 30%.

•Developed Python scripts for data preprocessing and integrated reporting pipelines with Power BI dashboards. Disha Athani

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