SoC/UVM Design Verification Engineer

ANKUR PANGHAL

+1-559-***-**** **************@*****.*** linkedin.com/in/ankur09

PROFESSIONAL SUMMARY

Design Verification Engineer with 5+ years of experience in ASIC and SoC verification using SystemVerilog and UVM. Experienced in developing reusable UVM verification environments, constrained random and directed testing, SystemVerilog Assertions (SVA), functional coverage, regression debugging, and coverage closure. Hands-on experience with AXI4, AHB/AHB-Lite, APB, and PCIe Gen5 based designs, including interconnect/crossbar and transaction layer verification. Proficient in VCS/Verdi debugging and Python/TCL scripting for regression and verification automation.

PROFESSIONAL EXPERIENCE

Design Verification Engineer

SoCtronics Technologies

Jan 2025 – Dec 2025 Santa Clara, CA, USA

• Performed functional verification of PCIe Gen5 Transaction Layer using SystemVerilog/UVM.

• Analyzed PCIe specifications and developed test scenarios for Transaction Layer features and corner cases.

• Verified TLPs, Memory Read/Write, Completions, tags, ordering, outstanding requests, and error scenarios.

• Developed test scenarios for TLP header/payload handling, request-completion flows, and end-to-end data integrity during memory transactions.

• Developed UVM sequences, scoreboards, SVA, and functional coverage for protocol and transaction-level checking.

• Executed regressions, analyzed functional coverage, and debugged protocol/RTL failures to drive verification closure.

• Reviewed simulation results, analyzed waveform dumps and log files, and isolated the root cause of functional failures during SoC verification.

• Automated regression and log analysis using Python/TCL and collaborated with RTL/design teams on root-cause analysis and bug resolution. Verification Engineer

NXP Semiconductors,

Jun 2019 – Jul 2023 Noida, UP, India

• Performed verification of AHB interconnect, developing SV/UVM testbench components and reusable verification sequences.

• Extracted verification features from design specifications and developed constrained-random/directed tests for arbitration, address decoding, bursts, wait states, and error responses.

• Developed SVA, scoreboards, and functional coverage for AHB protocol compliance and end-to-end transaction checking.

• Worked on verification of AXI4 crossbar using SV/UVM verification components.

• Verified arbitration, routing, bursts, transaction IDs, outstanding transactions, ordering, concurrent traffic, and backpressure across AXI4 interfaces.

• Developed targeted AXI4 test scenarios and coverage models for protocol corner cases and end-to-end data integrity.

• Executed regressions, analyzed functional coverage, and debugged RTL/testbench failures using Synopsys VCS and Verdi to drive verification closure.

• Participated in verification planning and test-plan reviews and collaborated with RTL designers to resolve functional and protocol issues. TECHNICAL SKILLS

Languages and HDL: SystemVerilog, Verilog, Python

Verification Methodology: UVM, Constrained-Random Verification (CRV), Directed Testing, UVM RAL, Scoreboards & Reference Models, SystemVerilog Assertions (SVA), Functional Coverage, Coverage Closure, Regression Debug & Failure Analysis Tools: Synopsys VCS, Verdi, Cadence Xcelium, Siemens Questa Protocols & Interfaces: AMBA AXI4, AHB/AHB-Lite, APB, PCIe Gen5 Design Concepts: Multi-Clock & Reset Verification, Clock Domain Crossing (CDC), FIFO Verification, Register & Interrupt Verification, UPF Concepts

Scripting & Automation: Python, TCL, Regression Automation EDUCATION

California State University

Master of Science, Electrical and Computer Engineering Fresno, CA, USA

Kurukshetra University

Bachelor of Technology, Electronics and Communication Engineering Kurukshetra, HR, India

**************@*****.***

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