| Distance: | Resume alert | Resumes 41 - 50 of 6087 |
Project Management Intern
Irvine, CA
... • Debugged hardware with VHDL/Verilog in Linux, reducing error rates and boosting system stability for low-cost sensing devices. Software Developer Intern Siemens Energy Schenectady, NY 06/2024 - 08/2024 • Automated XML parsing with Python scripts, ... - May 29
... • Debugged hardware with VHDL/Verilog in Linux, reducing error rates and boosting system stability for low-cost sensing devices. Software Developer Intern Siemens Energy Schenectady, NY 06/2024 - 08/2024 • Automated XML parsing with Python scripts, ... - May 29
Systems Engineer Electrical Engineering
Silver Spring, MD
... May 1988 - August 2000 FORD MOTOR, Dearborn, MI Software Systems Engineer ●Incorporated multiplex/communications host chip (Verilog, FPGA) into system module designs. ●Lead tester for J1850 rigor at Ford Motor Company. ●Wrote Software Requirements ... - May 29
... May 1988 - August 2000 FORD MOTOR, Dearborn, MI Software Systems Engineer ●Incorporated multiplex/communications host chip (Verilog, FPGA) into system module designs. ●Lead tester for J1850 rigor at Ford Motor Company. ●Wrote Software Requirements ... - May 29
Software Development Computer Engineering
Decatur, GA
... Technical Skills Techical Languages: Java, SQL, RISC V Assembly, MIPS Assembly, C, C++, VHDL, Python, Cuda, Verilog, C#. Developer Tools: Quartus, Visual Studio, Mbed Studio, IntelliJ, Eclipse, Linux (Ubuntu). Hardware Expertise: FPGAs, ... - May 29
... Technical Skills Techical Languages: Java, SQL, RISC V Assembly, MIPS Assembly, C, C++, VHDL, Python, Cuda, Verilog, C#. Developer Tools: Quartus, Visual Studio, Mbed Studio, IntelliJ, Eclipse, Linux (Ubuntu). Hardware Expertise: FPGAs, ... - May 29
Software Engineer Embedded
Buffalo, NY
... 16-bit Single-Cycle Processor Verilog, Vivado, Basys 3 FPGA Mar 2025 – Apr 2025 • Designed and implemented a 16-bit single-cycle, non-pipelined CPU supporting arithmetic, logic, memory, branch, and jump instructions. • Developed core modules ... - May 28
... 16-bit Single-Cycle Processor Verilog, Vivado, Basys 3 FPGA Mar 2025 – Apr 2025 • Designed and implemented a 16-bit single-cycle, non-pipelined CPU supporting arithmetic, logic, memory, branch, and jump instructions. • Developed core modules ... - May 28
M. Sc. in Electrical and Computer Engineering
Baltimore, MD
... suite (Word, Excel, PowerPoint, Outlook) Verilog Programming Arduino Programming Multisim AVR Studio S-edit Cadence Virtuoso Vivado Personal Skills Leadership skills set honed through high school class debates and collaborative project assignments. ... - May 26
... suite (Word, Excel, PowerPoint, Outlook) Verilog Programming Arduino Programming Multisim AVR Studio S-edit Cadence Virtuoso Vivado Personal Skills Leadership skills set honed through high school class debates and collaborative project assignments. ... - May 26
Project Lead Signal Processing
Houston, TX
... FPGA-Based Random Sequence Memorization Menttal Roles & Responsibilities: Project Lead Jan 2025 - May 2025 ● Developed 25+ FPGA Verilog modules to create a game with RNG, scoreboard, multi-user authentication, etc. ● Organized top/sub-level systems ... - May 23
... FPGA-Based Random Sequence Memorization Menttal Roles & Responsibilities: Project Lead Jan 2025 - May 2025 ● Developed 25+ FPGA Verilog modules to create a game with RNG, scoreboard, multi-user authentication, etc. ● Organized top/sub-level systems ... - May 23
High School Computer Engineering
Batavia, IL
... Hardware Description Languages: Experienced in Verilog and VHDL - May 23
... Hardware Description Languages: Experienced in Verilog and VHDL - May 23
Real-Time R D
United States
... Projects: tiny-BLE-Stat, AIDrawPen, Kocaeli University, Kocaeli, Turkey Master of Science in Electronic and Communication Engineering ● Transferred to Clarkson University, Potsdam, NY in Spring 2023 ● Computer Hardware Architecture, FPGA, Verilog, ... - May 21
... Projects: tiny-BLE-Stat, AIDrawPen, Kocaeli University, Kocaeli, Turkey Master of Science in Electronic and Communication Engineering ● Transferred to Clarkson University, Potsdam, NY in Spring 2023 ● Computer Hardware Architecture, FPGA, Verilog, ... - May 21
Senior Software Engineer
New York City, NY
... and Community Leadership May 2020 TECHNICAL SKILLS Programming Languages: Python, C/C++, Java, x86/64, System Verilog, JavaScript, Rust Soft: Group Dynamics, Conflict Resolution, People Management, Leadership Others: Tensorflow, Django, ... - May 20
... and Community Leadership May 2020 TECHNICAL SKILLS Programming Languages: Python, C/C++, Java, x86/64, System Verilog, JavaScript, Rust Soft: Group Dynamics, Conflict Resolution, People Management, Leadership Others: Tensorflow, Django, ... - May 20
Lead Principal Ic Design
Pembroke Pines, FL, 33025
... Verilog/RTL HDL design and verification. Tsmc 110nm, Xfab 350nm High Voltage, Nisshimbo 350nm, Magna 350nm Education: New Jersey Institute of Technology, Newark, NJ, USA. MS Electronics Engineering Tbilisi State University, BS and MS Radio physics ... - May 16
... Verilog/RTL HDL design and verification. Tsmc 110nm, Xfab 350nm High Voltage, Nisshimbo 350nm, Magna 350nm Education: New Jersey Institute of Technology, Newark, NJ, USA. MS Electronics Engineering Tbilisi State University, BS and MS Radio physics ... - May 16