| Distance: | Resume alert | Resumes 31 - 40 of 5855 |
GPU SoC Verification Engineer (UVM/CHI)
Houston, TX
... AXI3/4, AHB, APB, ARM CHI, SPI, I2C, I3C, UART, DDR Emulation / Prototyping: FPGA-based emulation bring-up (PYNQ-Z2 ARM Cortex-A9), Xilinx Vivado RTL-to-FPGA Languages & Tools: C, C++, SystemVerilog, Verilog, VHDL, Python, Perl, RISC-V Assembly; ... - Sep 10
... AXI3/4, AHB, APB, ARM CHI, SPI, I2C, I3C, UART, DDR Emulation / Prototyping: FPGA-based emulation bring-up (PYNQ-Z2 ARM Cortex-A9), Xilinx Vivado RTL-to-FPGA Languages & Tools: C, C++, SystemVerilog, Verilog, VHDL, Python, Perl, RISC-V Assembly; ... - Sep 10
PCIe Gen5 & I2C Protocol Verification Engineer
Portland, OR
... .*** +1-503-***-**** LinkedIn San Jose, CA PROFESSIONAL SUMMARY Design Verification Engineer with 3+ years of ASIC/IP verification experience specializing in PCIe Gen5 Data Link Layer and I2C protocol verification using System Verilog, UVM, and SVA. ... - Sep 10
... .*** +1-503-***-**** LinkedIn San Jose, CA PROFESSIONAL SUMMARY Design Verification Engineer with 3+ years of ASIC/IP verification experience specializing in PCIe Gen5 Data Link Layer and I2C protocol verification using System Verilog, UVM, and SVA. ... - Sep 10
ASIC SoC Verification Engineer
Sacramento, CA
... TECHNICAL SKILLS • Programming Languages: SystemVerilog, Verilog, C, C++, Embedded C, Python, Bash/Shell • ASIC & SoC Verification: RTL Verification, Functional Verification, IP Verification, SoC Verification, Constrained-Random Testing, Directed ... - Sep 10
... TECHNICAL SKILLS • Programming Languages: SystemVerilog, Verilog, C, C++, Embedded C, Python, Bash/Shell • ASIC & SoC Verification: RTL Verification, Functional Verification, IP Verification, SoC Verification, Constrained-Random Testing, Directed ... - Sep 10
Digital ASIC/FPGA Verification Engineer (UVM)
Raleigh, NC
PRASHRAY NAGAR Berkeley, California 919-***-**** *************@*****.*** LinkedIn GitHub Digital ASIC / FPGA Design Verification Engineer with hands-on experience in SystemVerilog/Verilog RTL microarchitecture, UVM-based functional verification, ... - Sep 10
PRASHRAY NAGAR Berkeley, California 919-***-**** *************@*****.*** LinkedIn GitHub Digital ASIC / FPGA Design Verification Engineer with hands-on experience in SystemVerilog/Verilog RTL microarchitecture, UVM-based functional verification, ... - Sep 10
Embedded Systems & Edge AI Engineer
Houston, TX
... SKILLS Languages: C/C++, Python, Rust (Embedded), Verilog, SystemVerilog, VHDL, Tcl, Assembly, Bash Embedded Systems & RTOS: ARM Cortex-M, STM32, ESP32, FreeRTOS, Zephyr RTOS, Embedded Linux, Bare-Metal Development, Real-Time Task Scheduling, ... - Sep 10
... SKILLS Languages: C/C++, Python, Rust (Embedded), Verilog, SystemVerilog, VHDL, Tcl, Assembly, Bash Embedded Systems & RTOS: ARM Cortex-M, STM32, ESP32, FreeRTOS, Zephyr RTOS, Embedded Linux, Bare-Metal Development, Real-Time Task Scheduling, ... - Sep 10
Senior ASIC/FPGA Design Verification Engineer
St. Louis, MO
Faizan Senior Design Verification Engineer **********@*****.*** 314-***-**** PROFESSIONAL SUMMARY •Senior Design Verification Engineer with 6+ years of experience in ASIC and FPGA verification using System Verilog and UVM methodologies across ... - Sep 10
Faizan Senior Design Verification Engineer **********@*****.*** 314-***-**** PROFESSIONAL SUMMARY •Senior Design Verification Engineer with 6+ years of experience in ASIC and FPGA verification using System Verilog and UVM methodologies across ... - Sep 10
SystemVerilog UVM Design Verification Engineer
San Jose, CA
... TECHNICAL SKILLS Hardware Description Languages: Verilog, SystemVerilog Verification: UVM, SystemVerilog OOP, SVA, constrained-random verification, functional coverage, code coverage, waveform debugging, regression debugging, formal verification ... - Sep 10
... TECHNICAL SKILLS Hardware Description Languages: Verilog, SystemVerilog Verification: UVM, SystemVerilog OOP, SVA, constrained-random verification, functional coverage, code coverage, waveform debugging, regression debugging, formal verification ... - Sep 10
RTL Verification & FPGA VLSI Engineer
Chicago, IL
... Skilled in Verilog, SystemVerilog, digital logic design, finite state machines, test- bench development, timing concepts, reset behavior, and design documentation. Experienced in reviewing design specifications, writing clean RTL logic, preparing ... - Sep 10
... Skilled in Verilog, SystemVerilog, digital logic design, finite state machines, test- bench development, timing concepts, reset behavior, and design documentation. Experienced in reviewing design specifications, writing clean RTL logic, preparing ... - Sep 10
AI Security Engineer Transitioning to Robotics
Maplewood, NJ
... SKILLS DevSecOps & Cloud: GitHub Actions, Jenkins, SonarQube, Snyk, Checkmarx, Fortify on Demand, Terraform, Docker, Git Programming: Python, Bash, PowerShell, C, C++, JavaScript/Node.js, C#, Go, SQL, Verilog, MATLAB, VBA Tools & Practices: Jira, ... - Sep 04
... SKILLS DevSecOps & Cloud: GitHub Actions, Jenkins, SonarQube, Snyk, Checkmarx, Fortify on Demand, Terraform, Docker, Git Programming: Python, Bash, PowerShell, C, C++, JavaScript/Node.js, C#, Go, SQL, Verilog, MATLAB, VBA Tools & Practices: Jira, ... - Sep 04
FPGA/RTL & Embedded Communication Systems Intern
Ho Chi Minh City, Vietnam
... Hands-on experience with Verilog HDL, Xilinx Vivado, PYNQ-Z2, AXI interfaces, C/C++, Python, MATLAB, and hardware-software integration through projects in modulation classification, FPGA DSP, neural-network acceleration, and ESP32-based AIoT systems ... - Sep 03
... Hands-on experience with Verilog HDL, Xilinx Vivado, PYNQ-Z2, AXI interfaces, C/C++, Python, MATLAB, and hardware-software integration through projects in modulation classification, FPGA DSP, neural-network acceleration, and ESP32-based AIoT systems ... - Sep 03