| Distance: | Resume alert | Resumes 31 - 40 of 5928 |
Electrical Engineer Product Development
Edmonton, AB, Canada
... SKILLS o Software: Python, C, C++, System Verilog, VHDL, MATLAB, RStudio, Assembly, LTSpice, Candence, SolidWorks, AutoCAD, Microsoft Office Suite (Excel, Word, PowerPoint, Outlook) o Hardware: Circuit Analysis, Microcontrollers (Arduino, MC9S12XE), ... - 2025 Nov 11
... SKILLS o Software: Python, C, C++, System Verilog, VHDL, MATLAB, RStudio, Assembly, LTSpice, Candence, SolidWorks, AutoCAD, Microsoft Office Suite (Excel, Word, PowerPoint, Outlook) o Hardware: Circuit Analysis, Microcontrollers (Arduino, MC9S12XE), ... - 2025 Nov 11
C++ Computer Scientist
Kennewick, WA
Michael Vincent 509-***-**** *******.*.*******@***.*** **** ********* ** ***** Summary Computer Scientist proficient in multiple computer programming languages, including C, C++, and Verilog. Strong understanding of data structures, digital circuits ... - 2025 Nov 04
Michael Vincent 509-***-**** *******.*.*******@***.*** **** ********* ** ***** Summary Computer Scientist proficient in multiple computer programming languages, including C, C++, and Verilog. Strong understanding of data structures, digital circuits ... - 2025 Nov 04
Design Engineer Electrical Engineering
Cedar Rapids, IA
... Programming Languages: Verilog, C, and Python. WORK EXPERIENCE Skyworks Solutions Inc, Cedar Rapids, IA. June 2025 – Present RF Design Engineer Co-op • Design and development TXDSM MCMs for mid-high band 5G/LTE applications, focusing on RF ... - 2025 Nov 02
... Programming Languages: Verilog, C, and Python. WORK EXPERIENCE Skyworks Solutions Inc, Cedar Rapids, IA. June 2025 – Present RF Design Engineer Co-op • Design and development TXDSM MCMs for mid-high band 5G/LTE applications, focusing on RF ... - 2025 Nov 02
Design Engineer Asic
United States
... Modeled in Verilog the whole chip and generated testing vectors for production testing. Timing closure for all designs using Synopsys Prime Time / Cadence Tempus to tape-out approximately 20 chips. o Read SPEF files generated by layout. o Used On ... - 2025 Nov 01
... Modeled in Verilog the whole chip and generated testing vectors for production testing. Timing closure for all designs using Synopsys Prime Time / Cadence Tempus to tape-out approximately 20 chips. o Read SPEF files generated by layout. o Used On ... - 2025 Nov 01
R D Quality Engineer
Plano, TX, 75074
... OS : Unix, Linux HDL Languages : Verilog, VHDL HVL Language : System Verilog Simulation Tools : Model-Sim, gcc compiler, gdb debugger, Verilog XL, NcVHDL, VCS, NcVerilog (Cadence- Affirma). Synthesis Tools : DC Shell Linting Tool : Leda (Synopsys) ... - 2025 Oct 29
... OS : Unix, Linux HDL Languages : Verilog, VHDL HVL Language : System Verilog Simulation Tools : Model-Sim, gcc compiler, gdb debugger, Verilog XL, NcVHDL, VCS, NcVerilog (Cadence- Affirma). Synthesis Tools : DC Shell Linting Tool : Leda (Synopsys) ... - 2025 Oct 29
Continuous Improvement Information Technology
Vancouver, BC, Canada
... ●Semiconductor: VHDL/Verilog to physic test. ●Database: MS SQL, MySQL, HDFS, Hive, Impala, CUDA, Spark, TensorFlow. ●Statistics software: R, Eviews, SAS, SPSS. CERTIFICATIONS ●Japan Information-Technology Engineer Skill Standards. ●Chartered ... - 2025 Oct 22
... ●Semiconductor: VHDL/Verilog to physic test. ●Database: MS SQL, MySQL, HDFS, Hive, Impala, CUDA, Spark, TensorFlow. ●Statistics software: R, Eviews, SAS, SPSS. CERTIFICATIONS ●Japan Information-Technology Engineer Skill Standards. ●Chartered ... - 2025 Oct 22
Engineering Intern Electrical
Paterson, NJ
... in Electrical Engineering SKILLS MATLAB, PLC Programming, Ladder Logic, AutoCAD Electrical, SolidWorks, Power BI, Verilog, C++, Python, Java, LTSpice, Multisim, Control Panel, SAP, Salesforce, LabVIEW, PSpice, Xilinx ISE/Vivado, Arduino; proficient ... - 2025 Oct 08
... in Electrical Engineering SKILLS MATLAB, PLC Programming, Ladder Logic, AutoCAD Electrical, SolidWorks, Power BI, Verilog, C++, Python, Java, LTSpice, Multisim, Control Panel, SAP, Salesforce, LabVIEW, PSpice, Xilinx ISE/Vivado, Arduino; proficient ... - 2025 Oct 08
Embedded Systems Software Development
Bhubaneswar, Odisha, India
... of a High Speed CML Divider FLIP-FLOP Technical Skills Design Tools: Cadence Virtuoso Programming & Simulation: MATLAB, Verilog, VHDL, C, C++ Core Expertise: VLSI Design, Embedded Systems, Digital Electronics, Circuit Simulation MS-Word, MS-Excel, ... - 2025 Sep 20
... of a High Speed CML Divider FLIP-FLOP Technical Skills Design Tools: Cadence Virtuoso Programming & Simulation: MATLAB, Verilog, VHDL, C, C++ Core Expertise: VLSI Design, Embedded Systems, Digital Electronics, Circuit Simulation MS-Word, MS-Excel, ... - 2025 Sep 20
Hands-On Design Engineer
Bengaluru, Karnataka, India
... Worked on RTL (Register Transfer Level) design and simulation using industry-standard HDLs such as Verilog or VHDL (specify the actual language used, if known). • Performed functional verification and debugging of VLSI modules using simulation tools ... - 2025 Sep 15
... Worked on RTL (Register Transfer Level) design and simulation using industry-standard HDLs such as Verilog or VHDL (specify the actual language used, if known). • Performed functional verification and debugging of VLSI modules using simulation tools ... - 2025 Sep 15
Computer Engineer
East Chicago, IN
... ACADEMIC EXPERIENCE: Individual Projects, West Lafayette, IN • Verilog & FGPA Drum Machine August 2022 – December 2022 Designed and programmed an FGPA Drum Machine, allowing users to play their own music combinations. • Analog Audio Equalizer & ... - 2025 Sep 11
... ACADEMIC EXPERIENCE: Individual Projects, West Lafayette, IN • Verilog & FGPA Drum Machine August 2022 – December 2022 Designed and programmed an FGPA Drum Machine, allowing users to play their own music combinations. • Analog Audio Equalizer & ... - 2025 Sep 11