| Distance: | Resume alert | Resumes 31 - 40 of 5877 |
Electronics & Communications Engineer - Java & Web Dev Focused
Hyderabad, Telangana, India
... +91-628******* ************@*****.*** Hyderabad, Telangana PROJECTS Design of VLSI Router using Arbiter, Crossbar and FIFO Designed a modular 5-port router using Verilog, focusing on FIFO-based buffering, arbitration logic, and crossbar switching. ... - Mar 07
... +91-628******* ************@*****.*** Hyderabad, Telangana PROJECTS Design of VLSI Router using Arbiter, Crossbar and FIFO Designed a modular 5-port router using Verilog, focusing on FIFO-based buffering, arbitration logic, and crossbar switching. ... - Mar 07
FPGA & Embedded Systems Engineer, PhD
Calgary, AB, Canada
... EUREKA/EURIPIDES SEAMOVES project Technical Skills FPGA & SoC Xilinx Zynq-7000, Vivado, Vitis, HLS, AXI4, DDR3/DDR4, DMA HDL Verilog, VHDL Embedded ARM processors, bare-metal, embedded Linux, FreeRTOS Interfaces SPI, I2C, UART, Ethernet, LVDS Tools ... - Mar 04
... EUREKA/EURIPIDES SEAMOVES project Technical Skills FPGA & SoC Xilinx Zynq-7000, Vivado, Vitis, HLS, AXI4, DDR3/DDR4, DMA HDL Verilog, VHDL Embedded ARM processors, bare-metal, embedded Linux, FreeRTOS Interfaces SPI, I2C, UART, Ethernet, LVDS Tools ... - Mar 04
Digital Design Engineering student for FPGA/ASIC/SoC
Brest, Finistere, France
... KEY PROJECTS UART-FIFO Interface IP Core with Avalon-MM Bus Integration Verilog, Quartus, TimeQuest, System Console Designed complete RTL datapath and control logic for UART-FIFO communication Implemented address decoding, register-based ... - Mar 04
... KEY PROJECTS UART-FIFO Interface IP Core with Avalon-MM Bus Integration Verilog, Quartus, TimeQuest, System Console Designed complete RTL datapath and control logic for UART-FIFO communication Implemented address decoding, register-based ... - Mar 04
Senior SDET Quality Assurance Engineer
San Jose, CA
... ● Skilled in updating and executing automated test scripts using Verilog XL, TCL/Expect, Spirent Fanfare iTest, and Python Scale Soak Test at overnight and long weekend SOAK in Non-disruptive and disruptive to improving test coverage and efficiency. ... - Mar 03
... ● Skilled in updating and executing automated test scripts using Verilog XL, TCL/Expect, Spirent Fanfare iTest, and Python Scale Soak Test at overnight and long weekend SOAK in Non-disruptive and disruptive to improving test coverage and efficiency. ... - Mar 03
SOFTWARE ENGINEER IV
United States
... SYSTEMS DESIGN ENGINEER MediaTek, India APRIL 2008 — AUGUST 2009 Developed CODA, an IDE for chipset designers to automate file generation (e.g., RTL Verilog, XML, C/C++ headers), enhancing productivity and consistency. Designed META CLI, a console ... - Feb 26
... SYSTEMS DESIGN ENGINEER MediaTek, India APRIL 2008 — AUGUST 2009 Developed CODA, an IDE for chipset designers to automate file generation (e.g., RTL Verilog, XML, C/C++ headers), enhancing productivity and consistency. Designed META CLI, a console ... - Feb 26
Electrical Engineer & Computer Engineer Student Leader
Bayonne, NJ
... hosted by IEEE-APS, IEEE North Jersey, and IEEE Photonics FPGA-Based CPU August 2024 - Nov 2024 a 32-bit CPU in VHDL and Verilog using Xilinx Vivado Analog Multiplexing System Printed Circuit Board August 2024 - Sept 2024 Designed a signal ... - Feb 25
... hosted by IEEE-APS, IEEE North Jersey, and IEEE Photonics FPGA-Based CPU August 2024 - Nov 2024 a 32-bit CPU in VHDL and Verilog using Xilinx Vivado Analog Multiplexing System Printed Circuit Board August 2024 - Sept 2024 Designed a signal ... - Feb 25
Electromagnetic Design & Motor Control Engineer
Chennai, Tamil Nadu, India
... Designed and implemented a PI controller on a DSP+FPGA board using Embedded C and Verilog to maintain constant output voltage regardless of load and input voltage variations. The Proposed model reduces the current rating of active devices and ... - Feb 25
... Designed and implemented a PI controller on a DSP+FPGA board using Embedded C and Verilog to maintain constant output voltage regardless of load and input voltage variations. The Proposed model reduces the current rating of active devices and ... - Feb 25
Data Analyst: SQL & BI Enthusiast with QA Flair
Atlanta, GA
... •Characterized 0.18u and 90nm standard cell libraries, custom IO cells using layout simulation flow at Best/Worst/nominal case corners as well as other corners using Adopt and performed QA on the generated Synopsys, Verilog behavioral models as ... - Feb 20
... •Characterized 0.18u and 90nm standard cell libraries, custom IO cells using layout simulation flow at Best/Worst/nominal case corners as well as other corners using Adopt and performed QA on the generated Synopsys, Verilog behavioral models as ... - Feb 20
ASIC/RTL design engineer
Hyderabad, Telangana, India
... KEY SKILLS - Programming Languages: C Verilog System Verilog. - EDA: RTL Simulation Synthesis and analysis(Synopsys Design Compiler, Fusion Compiler) - Scripting: TCL, Perl. - Core VLSI knowledge: RTL design, digital architecture, IP based design ... - Feb 15
... KEY SKILLS - Programming Languages: C Verilog System Verilog. - EDA: RTL Simulation Synthesis and analysis(Synopsys Design Compiler, Fusion Compiler) - Scripting: TCL, Perl. - Core VLSI knowledge: RTL design, digital architecture, IP based design ... - Feb 15
Electrical Design Engineer with Controls & HW Expertise
California City, CA
... mitigation, thermal management, ESD protection, board bring-up • Semiconductor & VLSI – Hardware Design & Verification: Verilog HDL, SystemVerilog, UVM, OVM, C, Python, FPGA programming, ASIC development, VLSI design, static timing analysis, mixed ... - Feb 12
... mitigation, thermal management, ESD protection, board bring-up • Semiconductor & VLSI – Hardware Design & Verification: Verilog HDL, SystemVerilog, UVM, OVM, C, Python, FPGA programming, ASIC development, VLSI design, static timing analysis, mixed ... - Feb 12