UCIe ASIC Protocol Verification Engineer

Sanjana Halavarthi Jagadeesha

279-***-**** # *********************@*****.*** ï linkedin.com/in/sanjana-hj § github.com/hjsanjana Education

California State University August 2023 – Dec 2025 Masters of Science in Electrical and Electronics Engineering,GPA:3.9 Sacramento, California PES University August 2019 – May 2023

Bachelors of Science in Electronics and communication Engineering,GPA:3.6 Bengaluru, India Experience

Western Semiconductor September 2026 – Present

ASIC Design Engineer Remote

• Own end-to-end UCIe protocol development and verification, driving architecture understanding, protocol-flow analysis, implementation, simulation, debugging, and validation across the UCIe stack

• Lead UCIe/PCIe interface development, translating UCIe specifications into RTL/verification requirements and developing robust test scenarios to validate protocol compliance, interoperability, and corner-case behavior. Information and Research Technology-CSUS March 2024 –Dec 2025 Graduate Student Assistant Sacramento CA

• Configured and optimized network switching modules to improve data throughput and system reliability.

• Collaborated with technical staff to troubleshoot hardware/network issues and support reliable system operation across shared infrastructure environments.

Projects

RISC-V CPU Pipeline Verification SystemVerilog, UVM, RISC-V, Synopsys VCS

• Developed a scalable UVM-based CPU validation environment for a pipelined RISC-V core targeting instruction decode, execution, forwarding, hazard detection, register write-back, and control-flow correctness.

• Generated constrained-random instruction streams stressing branch redirection, pipeline stalls, data dependencies, memory ordering, and exception-handling behavior to improve microarchitectural validation coverage. FPGA-Assisted Validation and Emulation Workflow Verilog, SystemVerilog, Python, Xilinx ISE, Linux

• Mapped synthesizable RTL modules into an FPGA-based prototype environment to validate functional behavior beyond RTL simulation and strengthen pre-silicon validation workflows.

• Performed waveform-driven debug and root-cause analysis for reset sequencing, timing mismatches, interface behavior, and data-integrity issues using hardware traces and Python-based validation scripts. Automated Regression Framework for SoC Verification Python, Bash, YAML, Synopsys VCS, Linux

• Built Python-based validation infrastructure supporting automated RTL simulation execution, testcase monitoring, log parsing, and regression management for large-scale CPU verification cycles.

• Developed scripting utilities for waveform-debug workflows, coverage tracking, and root-cause analysis of protocol ordering, transaction-completion, and memory-access failures during simulation regression runs. C++ Golden Reference Model with DPI-C Integration C++, SystemVerilog, DPI-C, UVM, Synopsys VCS

• Developed a C++ golden reference model and integrated it with a SystemVerilog/UVM testbench through DPI-C for expected-output comparison against RTL simulation results.

• Developed scoreboard-based behavioral checkers comparing RTL outputs against C++ reference-model predictions to improve debug accuracy and reduce manual waveform inspection. AXI4 Protocol Verification and Deadlock Detection SystemVerilog, UVM, SVA, Python, Synopsys VCS

• Built reusable UVM agents, monitors, scoreboards, and constrained-random stimulus to verify AXI4 burst transfers, ordering behavior, and data integrity.

• Authored SystemVerilog assertions to detect protocol violations and bounded-liveness failures, improving visibility into deadlock, response ordering, and transaction completion issues. PCIe Transaction Layer Verification with UVM SystemVerilog, UVM, PCIe, Synopsys VCS

• Developed a reusable UVM verification environment to validate PCIe Transaction Layer Packet handling for memory read/write transactions, payload variations, ordering rules, and malformed packet scenarios.

• Implemented constrained-random sequences, monitors, scoreboards, and functional coverage to verify packet correctness, error handling, and protocol-level transaction integrity. Technical Skills

• Verification: SystemVerilog, UVM, constrained-random verification, SVA, functional coverage, waveform debug

• Protocols/Architecture: DDR4, AXI4, PCIe, RISC-V, memory subsystem concepts

• Programming/Scripting: Python, Perl, C, C++, Bash

• Validation Platforms: FPGA-assisted validation, emulation exposure, hardware-assisted verification workflows

• Tools/Platforms: Synopsys VCS, Cadence Virtuoso, Xilinx ISE, Simulia CST, Matlab, Linux/UNIX

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