| Distance: | Resume alert | Resumes 1 - 10 of 5854 |
FPGA/VLSI Engineer - Smart Grid Protection
Ashburn, VA
... •Hands-on experience developing synthesizable RTL using Verilog, SystemVerilog, and VHDL for real-time processing and control applications. •Experience implementing FPGA-based electrical protection functions, including over-voltage, under-voltage, ... - Nov 09
... •Hands-on experience developing synthesizable RTL using Verilog, SystemVerilog, and VHDL for real-time processing and control applications. •Experience implementing FPGA-based electrical protection functions, including over-voltage, under-voltage, ... - Nov 09
RTL Design & Verification Intern Candidate
Mesa, AZ
... Proficient in Verilog/SystemVerilog, UVM fundamentals, ASIC design flows, and functional verification. CORE COMPETENCIES • HDLs & HVLs: Verilog, SystemVerilog, VHDL • Verification Fundamentals: UVM basics, testbench development, SystemVerilog ... - Nov 09
... Proficient in Verilog/SystemVerilog, UVM fundamentals, ASIC design flows, and functional verification. CORE COMPETENCIES • HDLs & HVLs: Verilog, SystemVerilog, VHDL • Verification Fundamentals: UVM basics, testbench development, SystemVerilog ... - Nov 09
Design Verification Engineer - UVM SVA
Mumbai, Maharashtra, India
... TECHNICAL SKILLS Languages: Verilog, SystemVerilog, SystemVerilog Assertions (SVA) Methodologies: Universal Verification Methodology (UVM), Constrained Random Verification (CRV), Assertion-Based Verification (ABV), Coverage-Driven Verification, ... - Nov 05
... TECHNICAL SKILLS Languages: Verilog, SystemVerilog, SystemVerilog Assertions (SVA) Methodologies: Universal Verification Methodology (UVM), Constrained Random Verification (CRV), Assertion-Based Verification (ABV), Coverage-Driven Verification, ... - Nov 05
Electrical Electronic Test & V&V Engineer
Los Angeles County, CA
... Waterfall Software Development Python, PERL, C&C++, Visual Basic, MATLAB, LabVIEW, VHDL, Verilog, SystemVerilog, Microprocessors EVT (Engineering Validation Test), DVT. V&V. Exploratory Methodology Application/Tools, System Testing, DOORS Database, ... - Nov 04
... Waterfall Software Development Python, PERL, C&C++, Visual Basic, MATLAB, LabVIEW, VHDL, Verilog, SystemVerilog, Microprocessors EVT (Engineering Validation Test), DVT. V&V. Exploratory Methodology Application/Tools, System Testing, DOORS Database, ... - Nov 04
SystemVerilog UVM Verification Engineer
Denton, TX, 76208
... SKILLS RTL Design: SystemVerilog, Verilog, Synthesizable RTL, Microarchitecture, FSMs, Datapaths, Control Logic, Clock & Reset Design Verification Methodologies: UVM, SystemVerilog Assertions (SVA), Constrained-Random Testing, Coverage-Driven ... - Nov 04
... SKILLS RTL Design: SystemVerilog, Verilog, Synthesizable RTL, Microarchitecture, FSMs, Datapaths, Control Logic, Clock & Reset Design Verification Methodologies: UVM, SystemVerilog Assertions (SVA), Constrained-Random Testing, Coverage-Driven ... - Nov 04
Design Verification Engineer (UVM/SystemVerilog)
Dublin, CA
Kartheek Morisetti *****************@*****.*** 945-***-**** Fremont, California LINKS LinkedIn: kartheekmorisetti SKILLS PROGRAMMING • System Verilog • UVM • PAV-UPF • PA-GLS • C/C++ • Verilog • Python/Perl/Shell DV SKILLS • Constraint Randomization ... - Nov 03
Kartheek Morisetti *****************@*****.*** 945-***-**** Fremont, California LINKS LinkedIn: kartheekmorisetti SKILLS PROGRAMMING • System Verilog • UVM • PAV-UPF • PA-GLS • C/C++ • Verilog • Python/Perl/Shell DV SKILLS • Constraint Randomization ... - Nov 03
Mixed-Signal SoC Verification Engineer
McKinney, TX
... TECHNICAL SKILLS Languages: SystemVerilog (UVM, SVA, DPI-C), Verilog, SystemC, C/C++, Assembly, Python, Perl, Shell (Bash), Tcl. Verification Methodologies: AMS-RNM Verification, Analog-Digital Boundary Verification, Constrained-Random Verification, ... - Nov 03
... TECHNICAL SKILLS Languages: SystemVerilog (UVM, SVA, DPI-C), Verilog, SystemC, C/C++, Assembly, Python, Perl, Shell (Bash), Tcl. Verification Methodologies: AMS-RNM Verification, Analog-Digital Boundary Verification, Constrained-Random Verification, ... - Nov 03
ASIC Verification Engineer Breaking RTL and Protocol Bugs
Milpitas, CA
... Custom RISC Processor Design Designed a 14-bit, 4-stage pipelined RISC processor in Verilog with a Von Neumann memory architecture, 4-way associative L1 cache, and memory-mapped I/O, and built a Python assembler to generate machine code and test ... - Nov 03
... Custom RISC Processor Design Designed a 14-bit, 4-stage pipelined RISC processor in Verilog with a Von Neumann memory architecture, 4-way associative L1 cache, and memory-mapped I/O, and built a Python assembler to generate machine code and test ... - Nov 03
GPU Design Verification Engineer
Sacramento, CA
BHAVYA REDDY GANDHETI California, CA,***** 971-***-**** ******************@*****.*** OBJECTIVE GPU Design Verification Engineer with experience in System Verilog, UVM, SVA, formal verification, RTL debugging, and functional coverage. Skilled in GPU ... - Nov 03
BHAVYA REDDY GANDHETI California, CA,***** 971-***-**** ******************@*****.*** OBJECTIVE GPU Design Verification Engineer with experience in System Verilog, UVM, SVA, formal verification, RTL debugging, and functional coverage. Skilled in GPU ... - Nov 03
UVM Design & Verification Engineer
Boston, MA
... of Engineering, Electrical and Electronics Engineering GPA: 3.4/4 TECHNICAL SKILLS • Programming Languages: SystemVerilog, Verilog, C++, Python, Shell/Bash • Protocols: AMBA (AXI4Full/Lite/Stream, AHB, APB), UART, SPI, I2C • Tools: Questa/ModelSim, ... - Nov 03
... of Engineering, Electrical and Electronics Engineering GPA: 3.4/4 TECHNICAL SKILLS • Programming Languages: SystemVerilog, Verilog, C++, Python, Shell/Bash • Protocols: AMBA (AXI4Full/Lite/Stream, AHB, APB), UART, SPI, I2C • Tools: Questa/ModelSim, ... - Nov 03