| Distance: | Resume alert | Resumes 1 - 10 of 6087 |
Electrical Engineering System Design
San Jose, CA
... Engineering, San Jose State University – San Jose, CA 3.39/4 Aug 2023 – May 2025 Course Work: Advanced Digital System Design and Synthesis, Soc Design & Verification with System Verilog, Logic Verification with UVM, Advanced Computer Architecture. ... - Jul 07
... Engineering, San Jose State University – San Jose, CA 3.39/4 Aug 2023 – May 2025 Course Work: Advanced Digital System Design and Synthesis, Soc Design & Verification with System Verilog, Logic Verification with UVM, Advanced Computer Architecture. ... - Jul 07
System Developer Embedded
Ho Chi Minh City, Vietnam
... Programming languages: Verilog HDL, C, C++, Python, MATLAB. Tools: Oracle VirtualBox, Quartus Prime, STM32CubeIDE. Soft Skills: Presentation, Problem-Solving, Critical Thinking. CERTIFICATIONS Certificate of course "STM32 Programming" of the FETEL. ... - Jul 07
... Programming languages: Verilog HDL, C, C++, Python, MATLAB. Tools: Oracle VirtualBox, Quartus Prime, STM32CubeIDE. Soft Skills: Presentation, Problem-Solving, Critical Thinking. CERTIFICATIONS Certificate of course "STM32 Programming" of the FETEL. ... - Jul 07
Design Engineer Circuit
San Jose, CA
... Languages: IBIS models, Verilog-A, HSpice, Python, Ocean scripting, TCL scripting, MATLAB, C, C++ Software: Cadence Virtuoso (ADE XL, Maestro, Layout XL), Ansys Totem, Ansys Helic, Matlab, Hspice, Cadence Allegro, JMP, Logisim, Avanwaves, Cosim ... - Jul 06
... Languages: IBIS models, Verilog-A, HSpice, Python, Ocean scripting, TCL scripting, MATLAB, C, C++ Software: Cadence Virtuoso (ADE XL, Maestro, Layout XL), Ansys Totem, Ansys Helic, Matlab, Hspice, Cadence Allegro, JMP, Logisim, Avanwaves, Cosim ... - Jul 06
Ts Sci Mixed Signal
San Jose, CA
... USA citizen DoD Cleared SAP TS SCI CI-Poly Secret SUMMARY: ● Peter has 18+ years of experience in digital logic and mixed signal analog design with proficiency in RTL transistor and device circuit design Verilog, VHDL, System Verilog, Design ... - Jul 04
... USA citizen DoD Cleared SAP TS SCI CI-Poly Secret SUMMARY: ● Peter has 18+ years of experience in digital logic and mixed signal analog design with proficiency in RTL transistor and device circuit design Verilog, VHDL, System Verilog, Design ... - Jul 04
R D Quality Engineer
Plano, TX, 75074
... OS : Unix, Linux HDL Languages : Verilog, VHDL HVL Language : System Verilog Simulation Tools : Model-Sim, gcc compiler, gdb debugger, Verilog XL, NcVHDL, VCS, NcVerilog (Cadence- Affirma). Synthesis Tools : DC Shell Linting Tool : Leda (Synopsys) ... - Jul 02
... OS : Unix, Linux HDL Languages : Verilog, VHDL HVL Language : System Verilog Simulation Tools : Model-Sim, gcc compiler, gdb debugger, Verilog XL, NcVHDL, VCS, NcVerilog (Cadence- Affirma). Synthesis Tools : DC Shell Linting Tool : Leda (Synopsys) ... - Jul 02
Electrical Engineering System Design
Calgary, AB, Canada
Vsevolod Olgin 587-***-**** ********.*****@*****.*** SKILLS Programming: Python, C, MATLAB, System Verilog. Hardware: PIC, AVR, ESP32, PCB design, Analog Circuits Design, Embedded System Design. Software: Quartus, Altium, LTspice, Fusion 360, MPLAB, ... - Jul 01
Vsevolod Olgin 587-***-**** ********.*****@*****.*** SKILLS Programming: Python, C, MATLAB, System Verilog. Hardware: PIC, AVR, ESP32, PCB design, Analog Circuits Design, Embedded System Design. Software: Quartus, Altium, LTspice, Fusion 360, MPLAB, ... - Jul 01
C++ Embedded Software
Bien Hoa, Dong Nai, Vietnam
... Able to read datasheets and basic circuit diagrams Digital & RTL Design: Familiar with Verilog HDL and RTL modeling. Able to design and simulate ALU, multiplexers, FSMs, using ModelSim and GTKWave Languages: English (basic), Vietnamese (native) ... - Jun 30
... Able to read datasheets and basic circuit diagrams Digital & RTL Design: Familiar with Verilog HDL and RTL modeling. Able to design and simulate ALU, multiplexers, FSMs, using ModelSim and GTKWave Languages: English (basic), Vietnamese (native) ... - Jun 30
Customer Service Technical Support
Sacramento, CA
... Graphic Design, Adobe Creative Cloud, Robotics, VEX environment, Command prompt utilization, Powershell, UI Design, Verilog, VHDL, Quartus Simulation Software, FPGA utilization, Circuit Building Soft Skills: Customer service, Arabic, English, ... - Jun 28
... Graphic Design, Adobe Creative Cloud, Robotics, VEX environment, Command prompt utilization, Powershell, UI Design, Verilog, VHDL, Quartus Simulation Software, FPGA utilization, Circuit Building Soft Skills: Customer service, Arabic, English, ... - Jun 28
Electronics Engineer, embedded systems and firmware
Scottsdale, AZ, 85260
... Debug GDB, JTAG, SWD, ITP, ICE, ROM EMULATOR, QEMU Algorithms ECC, CRC, LRC CAD OrCAD, P-Cad, ProCad, Eagle, Altium Designer Logic PAL, GAL, CPLD, FPGA, ASIC (HDL, RTL, Verilog, PALASM, ABEL, etc.) Memory NAND-FLASH, SPI FLASH, EPROM, EEPROM, DRAM, ... - Jun 23
... Debug GDB, JTAG, SWD, ITP, ICE, ROM EMULATOR, QEMU Algorithms ECC, CRC, LRC CAD OrCAD, P-Cad, ProCad, Eagle, Altium Designer Logic PAL, GAL, CPLD, FPGA, ASIC (HDL, RTL, Verilog, PALASM, ABEL, etc.) Memory NAND-FLASH, SPI FLASH, EPROM, EEPROM, DRAM, ... - Jun 23
Embedded systems engineer
Lee, MA
... Education University of Massachusetts Amherst Spring 2025 Bachelor of Science in Computer Engineering: GPA 3.11 Technical Skills Python programming, MATLAB, Microsoft Word, Excel, PowerPoint, C++, GDB, g++, Risc-V Assembly, Verilog, Linux systems, ... - Jun 23
... Education University of Massachusetts Amherst Spring 2025 Bachelor of Science in Computer Engineering: GPA 3.11 Technical Skills Python programming, MATLAB, Microsoft Word, Excel, PowerPoint, C++, GDB, g++, Risc-V Assembly, Verilog, Linux systems, ... - Jun 23