| Distance: | Resume alert | Resumes 1 - 10 of 5920 |
Process Technician
Houston, TX
... SKILLS Technical Skills: • Programming Languages: Java, C++, Python, Verilog, SQL • Software & Tools: Embedded systems programming, circuit design, FPGA development, Tableau, LabVIEW, MATLAB Languages: • English (Fluent) • Spanish (Fluent) - Mar 26
... SKILLS Technical Skills: • Programming Languages: Java, C++, Python, Verilog, SQL • Software & Tools: Embedded systems programming, circuit design, FPGA development, Tableau, LabVIEW, MATLAB Languages: • English (Fluent) • Spanish (Fluent) - Mar 26
Senior Network Engineer with TS Clearance
Lowell, MA
... WPI Undergraduate TA 2013- 2015 Teaching assistant for Embedded Computing in Engineering Design and Digital Circuit Design Lab Assistant/Office Hours: ●Assisted students with microcontroller and FPGA projects, including debugging C and Verilog code, ... - Mar 25
... WPI Undergraduate TA 2013- 2015 Teaching assistant for Embedded Computing in Engineering Design and Digital Circuit Design Lab Assistant/Office Hours: ●Assisted students with microcontroller and FPGA projects, including debugging C and Verilog code, ... - Mar 25
Multidisciplinary Mechatronics Engineer & Software Developer
Mexico City, Mexico
... Matplotlib, Numpy, OpenCV, SQLAlchemy, Unittest, Pytest, MicroPython, Django, etc.), Solidity, PowerShell, C, C++, C#, VHDL, Verilog, Assembly, Kotlin (Material Design, Jetpack, Room, BLE, Google Play Services), Java (SpringBoot), XML, MATLAB. ... - Mar 11
... Matplotlib, Numpy, OpenCV, SQLAlchemy, Unittest, Pytest, MicroPython, Django, etc.), Solidity, PowerShell, C, C++, C#, VHDL, Verilog, Assembly, Kotlin (Material Design, Jetpack, Room, BLE, Google Play Services), Java (SpringBoot), XML, MATLAB. ... - Mar 11
Staff communicatioon, multimedia DSP/FPGA engineer
San Gabriel, CA
... Altera SignalTap Math Software: OCTAVE, MATLAB, MATHCAD Version Control Software: ClearCase, CVS, GIT Language: C, C++, Assemblies, Python, (System)Verilog, VHDL Lab Equipments (Scope, Logic/Spectrum Analyzer, Sniffer, Protocol Analyzer) O.S. ... - Mar 10
... Altera SignalTap Math Software: OCTAVE, MATLAB, MATHCAD Version Control Software: ClearCase, CVS, GIT Language: C, C++, Assemblies, Python, (System)Verilog, VHDL Lab Equipments (Scope, Logic/Spectrum Analyzer, Sniffer, Protocol Analyzer) O.S. ... - Mar 10
Full-Stack Developer with Java/Spring Boot Expertise
Visakhapatnam, Andhra Pradesh, India
... Ltd • Worked on digital logic and Verilog fundamentals • Strengthened system-level and logical problem-solving skills EDUCATION B.Tech – Electronics & Communication Engineering (2021–2025) DNR College of Engineering & Technology, Bhimavaram CGPA: 7 ... - Mar 08
... Ltd • Worked on digital logic and Verilog fundamentals • Strengthened system-level and logical problem-solving skills EDUCATION B.Tech – Electronics & Communication Engineering (2021–2025) DNR College of Engineering & Technology, Bhimavaram CGPA: 7 ... - Mar 08
Electronics & Communications Engineer - Java & Web Dev Focused
Hyderabad, Telangana, India
... +91-628******* ************@*****.*** Hyderabad, Telangana PROJECTS Design of VLSI Router using Arbiter, Crossbar and FIFO Designed a modular 5-port router using Verilog, focusing on FIFO-based buffering, arbitration logic, and crossbar switching. ... - Mar 07
... +91-628******* ************@*****.*** Hyderabad, Telangana PROJECTS Design of VLSI Router using Arbiter, Crossbar and FIFO Designed a modular 5-port router using Verilog, focusing on FIFO-based buffering, arbitration logic, and crossbar switching. ... - Mar 07
FPGA & Embedded Systems Engineer, PhD
Calgary, AB, Canada
... EUREKA/EURIPIDES SEAMOVES project Technical Skills FPGA & SoC Xilinx Zynq-7000, Vivado, Vitis, HLS, AXI4, DDR3/DDR4, DMA HDL Verilog, VHDL Embedded ARM processors, bare-metal, embedded Linux, FreeRTOS Interfaces SPI, I2C, UART, Ethernet, LVDS Tools ... - Mar 04
... EUREKA/EURIPIDES SEAMOVES project Technical Skills FPGA & SoC Xilinx Zynq-7000, Vivado, Vitis, HLS, AXI4, DDR3/DDR4, DMA HDL Verilog, VHDL Embedded ARM processors, bare-metal, embedded Linux, FreeRTOS Interfaces SPI, I2C, UART, Ethernet, LVDS Tools ... - Mar 04
Digital Design Engineering student for FPGA/ASIC/SoC
Brest, Finistere, France
... KEY PROJECTS UART-FIFO Interface IP Core with Avalon-MM Bus Integration Verilog, Quartus, TimeQuest, System Console Designed complete RTL datapath and control logic for UART-FIFO communication Implemented address decoding, register-based ... - Mar 04
... KEY PROJECTS UART-FIFO Interface IP Core with Avalon-MM Bus Integration Verilog, Quartus, TimeQuest, System Console Designed complete RTL datapath and control logic for UART-FIFO communication Implemented address decoding, register-based ... - Mar 04
Senior SDET Quality Assurance Engineer
San Jose, CA
... ● Skilled in updating and executing automated test scripts using Verilog XL, TCL/Expect, Spirent Fanfare iTest, and Python Scale Soak Test at overnight and long weekend SOAK in Non-disruptive and disruptive to improving test coverage and efficiency. ... - Mar 03
... ● Skilled in updating and executing automated test scripts using Verilog XL, TCL/Expect, Spirent Fanfare iTest, and Python Scale Soak Test at overnight and long weekend SOAK in Non-disruptive and disruptive to improving test coverage and efficiency. ... - Mar 03
SOFTWARE ENGINEER IV
United States
... SYSTEMS DESIGN ENGINEER MediaTek, India APRIL 2008 — AUGUST 2009 Developed CODA, an IDE for chipset designers to automate file generation (e.g., RTL Verilog, XML, C/C++ headers), enhancing productivity and consistency. Designed META CLI, a console ... - Feb 26
... SYSTEMS DESIGN ENGINEER MediaTek, India APRIL 2008 — AUGUST 2009 Developed CODA, an IDE for chipset designers to automate file generation (e.g., RTL Verilog, XML, C/C++ headers), enhancing productivity and consistency. Designed META CLI, a console ... - Feb 26