| Distance: | Resume alert | Resumes 1 - 10 of 5894 |
Design Verification Engineer Candidate with Hardware Experience
New Providence, NJ
... RTL-Coding EDUCATION Bachelor of Technology Electrical and Electronics Engineering Aug 2008 - May 2012 University of JNTU India GPA: 3.5 / 4.0 SKILLS Programming Languages: Verilog (Certified), System Verilog (Certified), System Verilog Assertions. ... - May 29
... RTL-Coding EDUCATION Bachelor of Technology Electrical and Electronics Engineering Aug 2008 - May 2012 University of JNTU India GPA: 3.5 / 4.0 SKILLS Programming Languages: Verilog (Certified), System Verilog (Certified), System Verilog Assertions. ... - May 29
Frontend Developer Intern / Fresher Resume
Boston, GA, 31629
... SKILLS Technical Skills Languages Java, C, Python, HTML, CSS Embedded Systems Arduino, ESP32, ESP8266, PIC16F877A, Atmega32, Embedded C, AVR, ARM Cortex-M FPGA / Digital Design Altera (CA), Verilog, VHDL IoT & Protocols MQTT, REST API, Flask-based ... - May 27
... SKILLS Technical Skills Languages Java, C, Python, HTML, CSS Embedded Systems Arduino, ESP32, ESP8266, PIC16F877A, Atmega32, Embedded C, AVR, ARM Cortex-M FPGA / Digital Design Altera (CA), Verilog, VHDL IoT & Protocols MQTT, REST API, Flask-based ... - May 27
FPGA & Embedded Systems Engineer Fresher/Intern candidate
Hoa Khanh Tay, Long An, Vietnam
... motor control, UART communication, and input handling Team-based design, testing, and validation FPGA Digital Lock (Verilog, Quartus) Designed a digital lock system on FPGA using Verilog in Quartus Implemented password logic and I/O control ... - May 22
... motor control, UART communication, and input handling Team-based design, testing, and validation FPGA Digital Lock (Verilog, Quartus) Designed a digital lock system on FPGA using Verilog in Quartus Implemented password logic and I/O control ... - May 22
Global IT & Data Analytics Leader seeking new challenges
Banqiao District, New Taipei City, Taiwan
... Html, PHP, ASP, JSP), XML, Parallel & Distributed simulation, OpenMP, MPI, SQL Server, MATLAB, CVS, Solaris, TCP, MS office, Verilog, VHDL, Processor simulator, Embedded system design, Real time system, System on Chip (SoC), Discrete-time signal ... - May 21
... Html, PHP, ASP, JSP), XML, Parallel & Distributed simulation, OpenMP, MPI, SQL Server, MATLAB, CVS, Solaris, TCP, MS office, Verilog, VHDL, Processor simulator, Embedded system design, Real time system, System on Chip (SoC), Discrete-time signal ... - May 21
RTL Design Engineer
India
... Proficient in Verilog/VHDL for RTL development of complex digital designs and mulƟ-clock domain systems. Experienced in Xilinx Vivado and QuestaSim for design, simulaƟon, and debugging. Hands-on experience with Xilinx Zynq-7000 and Zynq UltraScale ... - May 14
... Proficient in Verilog/VHDL for RTL development of complex digital designs and mulƟ-clock domain systems. Experienced in Xilinx Vivado and QuestaSim for design, simulaƟon, and debugging. Hands-on experience with Xilinx Zynq-7000 and Zynq UltraScale ... - May 14
Technical Talent Acquisition Specialist with 9+ Years Experience
Ahmedabad, Gujarat, India
... Manage full-cycle recruitment for semiconductor roles across: VLSI / ASIC / FPGA Design and Screen candidates on Design concepts (RTL, Verilog, SystemVerilog). Working on different IT as well as non-IT requirements such as System Engineer, FPGA ... - May 13
... Manage full-cycle recruitment for semiconductor roles across: VLSI / ASIC / FPGA Design and Screen candidates on Design concepts (RTL, Verilog, SystemVerilog). Working on different IT as well as non-IT requirements such as System Engineer, FPGA ... - May 13
Electrical & Computer Engineering student with ASIC/FPGA focus
Pittsburgh, PA
... ASIC Design Project (18-244 Tapeout)Carnegie Mellon University -Designed and verified RTL for a custom digital system using Verilog/SystemVerilog -Executed full ASIC flow: synthesis, place & route, and timing analysis using modern chip design tools ... - May 11
... ASIC Design Project (18-244 Tapeout)Carnegie Mellon University -Designed and verified RTL for a custom digital system using Verilog/SystemVerilog -Executed full ASIC flow: synthesis, place & route, and timing analysis using modern chip design tools ... - May 11
Electrical & Computer Engineering-VLSI & ASIC Specialist
Chandler, AZ
... Simulation Tools: Cadence Virtuoso, Cadence Innovus, HSPICE, LTSpice, MATLAB, AutoCAD Programming and HDL: Embedded C, Python, Verilog Automation Tools: Automation Anywhere Software, Drake Tax Software Certifications: Automation Anywhere Certified ... - May 05
... Simulation Tools: Cadence Virtuoso, Cadence Innovus, HSPICE, LTSpice, MATLAB, AutoCAD Programming and HDL: Embedded C, Python, Verilog Automation Tools: Automation Anywhere Software, Drake Tax Software Certifications: Automation Anywhere Certified ... - May 05
FPGA Engineer with Verification and Debug Expertise
Santa Clara, CA
... automotive domains, working closely with cross-functional engineering teams Strong expertise in writing synthesizable RTL using Verilog/SystemVerilog with focus on modular, scalable, and reusable design practices Designed and implemented UVM-based ... - Apr 29
... automotive domains, working closely with cross-functional engineering teams Strong expertise in writing synthesizable RTL using Verilog/SystemVerilog with focus on modular, scalable, and reusable design practices Designed and implemented UVM-based ... - Apr 29
Embedded Systems Engineer Intern Candidate
Visakhapatnam, Andhra Pradesh, India
... SKILLS 1 Digital Electronics: Boolean Algebra, K-Maps, Flip-Flops, Counters 2 Embedded Systems: Arduino, ESP32, I2C, UART 3 Programming: C, C++, Python (Basics) 4 HDL: Verilog (Basics) 5 Tools: Arduino IDE, Tinkercad, Wokwi, GitHub 6 Sensors: ... - Apr 24
... SKILLS 1 Digital Electronics: Boolean Algebra, K-Maps, Flip-Flops, Counters 2 Embedded Systems: Arduino, ESP32, I2C, UART 3 Programming: C, C++, Python (Basics) 4 HDL: Verilog (Basics) 5 Tools: Arduino IDE, Tinkercad, Wokwi, GitHub 6 Sensors: ... - Apr 24