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Electrical Engineer with FPGA and Hardware Expertise

Vienna, VA
... Computer Skills ALDEC Active HDL, Altium Designer, Cadence, Mentor Graphics DxDesigner Schematic Tool, Verilog, VHDL, ORCAD, Xilinx Design Tools, ModelSim, Excel, Microsoft Word, Adobe Acrobat, PowerPoint, Visio, Oscilloscope, HP Logic Analyzer, ... - Nov 19

Full-Stack Engineer with Cloud & ML Focus

Huntington, WV
... Technical Skills _ Languages: Python, C++, C, Java, C#, Go, Lua, JavaScript, SQL, Verilog Frameworks/Tools: PyTorch, TensorFlow, TVM, React, Node.js, Git, Azure, Unreal Engine 5, Blender, MongoDB, SQL Server, OpenCV, Wireshark Hardware/Systems: ... - Nov 17

Embedded Systems Engineer - Hardware & FPGA Focus

Cypress, CA
... Experience based on projects pertaining to Embedded Systems, FPGAs, Python, Verilog/VHDL, and electrical assembly. Able to accomplish tasks in a professional, organized, and strategic manner while exercising great communication skills. Experience RF ... - Nov 15

Electrical Engineer Product Development

Edmonton, AB, Canada
... SKILLS o Software: Python, C, C++, System Verilog, VHDL, MATLAB, RStudio, Assembly, LTSpice, Candence, SolidWorks, AutoCAD, Microsoft Office Suite (Excel, Word, PowerPoint, Outlook) o Hardware: Circuit Analysis, Microcontrollers (Arduino, MC9S12XE), ... - Nov 11

C++ Computer Scientist

Kennewick, WA
Michael Vincent 509-***-**** *******.*.*******@***.*** **** ********* ** ***** Summary Computer Scientist proficient in multiple computer programming languages, including C, C++, and Verilog. Strong understanding of data structures, digital circuits ... - Nov 04

Design Engineer Electrical Engineering

Cedar Rapids, IA
... Programming Languages: Verilog, C, and Python. WORK EXPERIENCE Skyworks Solutions Inc, Cedar Rapids, IA. June 2025 – Present RF Design Engineer Co-op • Design and development TXDSM MCMs for mid-high band 5G/LTE applications, focusing on RF ... - Nov 02

Design Engineer Asic

United States
... Modeled in Verilog the whole chip and generated testing vectors for production testing. Timing closure for all designs using Synopsys Prime Time / Cadence Tempus to tape-out approximately 20 chips. o Read SPEF files generated by layout. o Used On ... - Nov 01

R D Quality Engineer

Plano, TX, 75074
... OS : Unix, Linux HDL Languages : Verilog, VHDL HVL Language : System Verilog Simulation Tools : Model-Sim, gcc compiler, gdb debugger, Verilog XL, NcVHDL, VCS, NcVerilog (Cadence- Affirma). Synthesis Tools : DC Shell Linting Tool : Leda (Synopsys) ... - Oct 29

Continuous Improvement Information Technology

Vancouver, BC, Canada
... ●Semiconductor: VHDL/Verilog to physic test. ●Database: MS SQL, MySQL, HDFS, Hive, Impala, CUDA, Spark, TensorFlow. ●Statistics software: R, Eviews, SAS, SPSS. CERTIFICATIONS ●Japan Information-Technology Engineer Skill Standards. ●Chartered ... - Oct 22

Engineering Intern Electrical

Paterson, NJ
... in Electrical Engineering SKILLS MATLAB, PLC Programming, Ladder Logic, AutoCAD Electrical, SolidWorks, Power BI, Verilog, C++, Python, Java, LTSpice, Multisim, Control Panel, SAP, Salesforce, LabVIEW, PSpice, Xilinx ISE/Vivado, Arduino; proficient ... - Oct 08
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