| Distance: | Resume alert | Resumes 1 - 10 of 5859 |
Design Verification Engineer (UVM, SV, Python)
Fort Collins, CO
... GPA: 3.62/4.0 Jamia Hamdard Delhi, India Jul 2017 – Jun 2021 TECHNICAL SKILLS HDL (Hardware Description Languages): Verilog, SystemVerilog Programming Languages: Python, C/C++ Protocols: AMBA AXI, AMBA AHB, APB, I2C, SPI, UART, USART EDA Tools ... - Sep 17
... GPA: 3.62/4.0 Jamia Hamdard Delhi, India Jul 2017 – Jun 2021 TECHNICAL SKILLS HDL (Hardware Description Languages): Verilog, SystemVerilog Programming Languages: Python, C/C++ Protocols: AMBA AXI, AMBA AHB, APB, I2C, SPI, UART, USART EDA Tools ... - Sep 17
RTL Verification Engineer (UVM/SystemVerilog)
Grapevine, TX
... • Tools: Cadence Virtuoso, Spectre, Xilinx Vivado, ModelSim, ADS, Synopsys-VCS, Verdi, XA, Primesim, Primewave • Programming: Verilog, VHDL, SystemVerilog, UVM, UVM-RAL, Verilog-A/MS • Analog Skills: Analog MOS transistor models, Current mirrors, ... - Sep 16
... • Tools: Cadence Virtuoso, Spectre, Xilinx Vivado, ModelSim, ADS, Synopsys-VCS, Verdi, XA, Primesim, Primewave • Programming: Verilog, VHDL, SystemVerilog, UVM, UVM-RAL, Verilog-A/MS • Analog Skills: Analog MOS transistor models, Current mirrors, ... - Sep 16
RTL Design & Verification Engineer
Aurora, CO, 80014
... Strong in SystemVerilog, Verilog, RTL design, microarchitecture, UVM, SVA, constrained-random testing, coverage-driven verification, and simulation debug, with experience across block, subsystem, and SoC-level verification. Proficient with Synopsys ... - Sep 15
... Strong in SystemVerilog, Verilog, RTL design, microarchitecture, UVM, SVA, constrained-random testing, coverage-driven verification, and simulation debug, with experience across block, subsystem, and SoC-level verification. Proficient with Synopsys ... - Sep 15
SoC/UVM Design Verification Engineer
Bareilly, Uttar Pradesh, India
... TECHNICAL SKILLS Languages and HDL: SystemVerilog, Verilog, Python Verification Methodology: UVM, Constrained-Random Verification (CRV), Directed Testing, UVM RAL, Scoreboards & Reference Models, SystemVerilog Assertions (SVA), Functional Coverage, ... - Sep 10
... TECHNICAL SKILLS Languages and HDL: SystemVerilog, Verilog, Python Verification Methodology: UVM, Constrained-Random Verification (CRV), Directed Testing, UVM RAL, Scoreboards & Reference Models, SystemVerilog Assertions (SVA), Functional Coverage, ... - Sep 10
GPU SoC Verification Engineer (UVM/CHI)
Houston, TX
... AXI3/4, AHB, APB, ARM CHI, SPI, I2C, I3C, UART, DDR Emulation / Prototyping: FPGA-based emulation bring-up (PYNQ-Z2 ARM Cortex-A9), Xilinx Vivado RTL-to-FPGA Languages & Tools: C, C++, SystemVerilog, Verilog, VHDL, Python, Perl, RISC-V Assembly; ... - Sep 10
... AXI3/4, AHB, APB, ARM CHI, SPI, I2C, I3C, UART, DDR Emulation / Prototyping: FPGA-based emulation bring-up (PYNQ-Z2 ARM Cortex-A9), Xilinx Vivado RTL-to-FPGA Languages & Tools: C, C++, SystemVerilog, Verilog, VHDL, Python, Perl, RISC-V Assembly; ... - Sep 10
PCIe Gen5 & I2C Protocol Verification Engineer
Portland, OR
... .*** +1-503-***-**** LinkedIn San Jose, CA PROFESSIONAL SUMMARY Design Verification Engineer with 3+ years of ASIC/IP verification experience specializing in PCIe Gen5 Data Link Layer and I2C protocol verification using System Verilog, UVM, and SVA. ... - Sep 10
... .*** +1-503-***-**** LinkedIn San Jose, CA PROFESSIONAL SUMMARY Design Verification Engineer with 3+ years of ASIC/IP verification experience specializing in PCIe Gen5 Data Link Layer and I2C protocol verification using System Verilog, UVM, and SVA. ... - Sep 10
ASIC SoC Verification Engineer
Sacramento, CA
... TECHNICAL SKILLS • Programming Languages: SystemVerilog, Verilog, C, C++, Embedded C, Python, Bash/Shell • ASIC & SoC Verification: RTL Verification, Functional Verification, IP Verification, SoC Verification, Constrained-Random Testing, Directed ... - Sep 10
... TECHNICAL SKILLS • Programming Languages: SystemVerilog, Verilog, C, C++, Embedded C, Python, Bash/Shell • ASIC & SoC Verification: RTL Verification, Functional Verification, IP Verification, SoC Verification, Constrained-Random Testing, Directed ... - Sep 10
Digital ASIC/FPGA Verification Engineer (UVM)
Raleigh, NC
PRASHRAY NAGAR Berkeley, California 919-***-**** *************@*****.*** LinkedIn GitHub Digital ASIC / FPGA Design Verification Engineer with hands-on experience in SystemVerilog/Verilog RTL microarchitecture, UVM-based functional verification, ... - Sep 10
PRASHRAY NAGAR Berkeley, California 919-***-**** *************@*****.*** LinkedIn GitHub Digital ASIC / FPGA Design Verification Engineer with hands-on experience in SystemVerilog/Verilog RTL microarchitecture, UVM-based functional verification, ... - Sep 10
Embedded Systems & Edge AI Engineer
Houston, TX
... SKILLS Languages: C/C++, Python, Rust (Embedded), Verilog, SystemVerilog, VHDL, Tcl, Assembly, Bash Embedded Systems & RTOS: ARM Cortex-M, STM32, ESP32, FreeRTOS, Zephyr RTOS, Embedded Linux, Bare-Metal Development, Real-Time Task Scheduling, ... - Sep 10
... SKILLS Languages: C/C++, Python, Rust (Embedded), Verilog, SystemVerilog, VHDL, Tcl, Assembly, Bash Embedded Systems & RTOS: ARM Cortex-M, STM32, ESP32, FreeRTOS, Zephyr RTOS, Embedded Linux, Bare-Metal Development, Real-Time Task Scheduling, ... - Sep 10
Senior ASIC/FPGA Design Verification Engineer
St. Louis, MO
Faizan Senior Design Verification Engineer **********@*****.*** 314-***-**** PROFESSIONAL SUMMARY •Senior Design Verification Engineer with 6+ years of experience in ASIC and FPGA verification using System Verilog and UVM methodologies across ... - Sep 10
Faizan Senior Design Verification Engineer **********@*****.*** 314-***-**** PROFESSIONAL SUMMARY •Senior Design Verification Engineer with 6+ years of experience in ASIC and FPGA verification using System Verilog and UVM methodologies across ... - Sep 10