| Distance: | Resume alert | Resumes 1 - 10 of 5850 |
ASIC SoC Design Verification Engineer
Hyderabad, Telangana, India
... Technical Skills: Verification Languages SystemVerilog, Verilog Methodologies UVM, Constrained-Random Verification, Coverage-Driven Verification UVM Components Sequence, Sequencer, Driver, Monitor, Agent, Scoreboard, Environment Assertions SVA, ... - Oct 12
... Technical Skills: Verification Languages SystemVerilog, Verilog Methodologies UVM, Constrained-Random Verification, Coverage-Driven Verification UVM Components Sequence, Sequencer, Driver, Monitor, Agent, Scoreboard, Environment Assertions SVA, ... - Oct 12
18-Year HR & Talent Acquisition Strategist
Nangavalli, Tamil Nadu, India
... Semi-Conductor Skills Recruited Physical Design, ASIC Design, ASIC Verification, RTL Design, RTL Verification, Verilog etc. Distributed Computing - Nvidia, Remote DMA, ARM, HPC etc. Embedded C Linux – Embedded, C, C++, Linux, ARM, RTOS, IoT etc. ... - Oct 10
... Semi-Conductor Skills Recruited Physical Design, ASIC Design, ASIC Verification, RTL Design, RTL Verification, Verilog etc. Distributed Computing - Nvidia, Remote DMA, ARM, HPC etc. Embedded C Linux – Embedded, C, C++, Linux, ARM, RTOS, IoT etc. ... - Oct 10
Pre-Silicon Verification Engineer (UVM/SystemVerilog)
Cincinnati, OH
... Mopuru 513-***-**** *****************@*****.*** linkedin.com/in/tharunrm github.com/Tharunreddym TECHNICAL SKILLS SystemVerilog, Verilog, SystemVerilog OOP, UVM, C++, C, Python, Embedded C, Linux, Git Pre-Silicon Ver- ification, RTL Verification, ... - Oct 05
... Mopuru 513-***-**** *****************@*****.*** linkedin.com/in/tharunrm github.com/Tharunreddym TECHNICAL SKILLS SystemVerilog, Verilog, SystemVerilog OOP, UVM, C++, C, Python, Embedded C, Linux, Git Pre-Silicon Ver- ification, RTL Verification, ... - Oct 05
Design Verification Engineer - UVM & SVA
Hyderabad, Telangana, India
... Coverage, Formal Verification, Testbench Development, Verification/Test Planning, Fault Simulation • HDL / Languages: Verilog, SystemVerilog, VHDL, C, C++, Python, TCL, Perl • Protocols: AXI4, AHB, APB, CHI • DFT: ATPG (D-algorithm, PODEM), JTAG ... - Sep 29
... Coverage, Formal Verification, Testbench Development, Verification/Test Planning, Fault Simulation • HDL / Languages: Verilog, SystemVerilog, VHDL, C, C++, Python, TCL, Perl • Protocols: AXI4, AHB, APB, CHI • DFT: ATPG (D-algorithm, PODEM), JTAG ... - Sep 29
VLSI & Embedded Systems Engineer
Bengaluru, Karnataka, India
SRUJAN N M +91-963******* ***************@*****.*** Professional Summary VLSI and Embedded Systems Engineer with knowledge of Verilog, VHDL, SystemVerilog, CMOS design, FPGA implementation, Embedded C, ARM-based development, RTOS, hardware- software ... - Sep 26
SRUJAN N M +91-963******* ***************@*****.*** Professional Summary VLSI and Embedded Systems Engineer with knowledge of Verilog, VHDL, SystemVerilog, CMOS design, FPGA implementation, Embedded C, ARM-based development, RTOS, hardware- software ... - Sep 26
ASIC SoC Design Verification Engineer
Richardson, TX
... TECHNICAL SKILLS • Languages: Verilog, SystemVerilog, UVM, Perl, C/C++, Python, Java, MIPS. • Verification Methodologies: Testbench Architecture Development, Constraint-Random Verification, Assertion-Based Verification (ABV), Functional and Code ... - Sep 24
... TECHNICAL SKILLS • Languages: Verilog, SystemVerilog, UVM, Perl, C/C++, Python, Java, MIPS. • Verification Methodologies: Testbench Architecture Development, Constraint-Random Verification, Assertion-Based Verification (ABV), Functional and Code ... - Sep 24
UCIe ASIC Protocol Verification Engineer
Phoenixville, PA
... FPGA-Assisted Validation and Emulation Workflow Verilog, SystemVerilog, Python, Xilinx ISE, Linux • Mapped synthesizable RTL modules into an FPGA-based prototype environment to validate functional behavior beyond RTL simulation and strengthen pre ... - Sep 24
... FPGA-Assisted Validation and Emulation Workflow Verilog, SystemVerilog, Python, Xilinx ISE, Linux • Mapped synthesizable RTL modules into an FPGA-based prototype environment to validate functional behavior beyond RTL simulation and strengthen pre ... - Sep 24
Senior Product Development & ATE Engineering Leader
Pune, Maharashtra, India
... Technology Well versed with MIL-Std-704D, MIL-Std-461C, MIL-Std-810D and DO160G certification standards Software Skills Verilog, VHDL, SystemC Xilinx ISE(12.0), ModelSim(v6.1), NC_SystemC(2.0), Cadence_ldv (v 3.2), Synopsis DC PSPICE, ORCAD (v9.0) ... - Sep 23
... Technology Well versed with MIL-Std-704D, MIL-Std-461C, MIL-Std-810D and DO160G certification standards Software Skills Verilog, VHDL, SystemC Xilinx ISE(12.0), ModelSim(v6.1), NC_SystemC(2.0), Cadence_ldv (v 3.2), Synopsis DC PSPICE, ORCAD (v9.0) ... - Sep 23
ASIC/VLSI Verification & RTL-to-GDSII Engineer
Irving, TX
... TECHNICAL SKILLS HDL & Verification: Verilog, SystemVerilog, UVM Testbench Development, Constrained-Random & Coverage-Driven Verification, Assertion-Based Verification EDA & Simulation Tools: Synopsys VCS, Verdi, Xschem, ngspice, Magic VLSI, KLayout ... - Sep 21
... TECHNICAL SKILLS HDL & Verification: Verilog, SystemVerilog, UVM Testbench Development, Constrained-Random & Coverage-Driven Verification, Assertion-Based Verification EDA & Simulation Tools: Synopsys VCS, Verdi, Xschem, ngspice, Magic VLSI, KLayout ... - Sep 21
Design Verification Engineer
Houston, TX
... Strong knowledge of SystemVerilog, Verilog, VHDL, C, C++, Python, Perl, Tcl, and Shell scripting. Experienced in developing UVM-based testbenches, constrained random verification (CRV), & functional verification. Hands-on experience with ... - Sep 19
... Strong knowledge of SystemVerilog, Verilog, VHDL, C, C++, Python, Perl, Tcl, and Shell scripting. Experienced in developing UVM-based testbenches, constrained random verification (CRV), & functional verification. Hands-on experience with ... - Sep 19