RTL Verification Engineer (UVM/SystemVerilog)

Rashid Syed

**************@*****.*** • LinkedIn • 940-***-****

PROFESSIONAL SUMMARY

Design Verification Engineer with experience in RTL verification using SystemVerilog and UVM, and internship exposure to Analog and Mixed-Signal (AMS) verification. Proficient in developing UVM-based verification environments including sequences, drivers, monitors, and scoreboards. Skilled in debugging functional and protocol issues using simulation, waveform analysis, and assertions. Familiar with memory controller verification, SDRAM timing constraints, and interface protocols such as APB and AXI. EDUCATION

• MS - Electrical Engineering GPA: 4.0/4.0 Jul 2023 University of North Texas at Denton, Texas

• BE - Electronics & Communication Engineering GPA: 8.06/10 Apr 2019 RMK Engineering College, Chennai, India

RELEVANT COURSEWORK

Digital IC Design, Digital Design Techniques, Hardware Design Methodologies of ASIC and FPGA, Analog IC Design TECHNICAL SKILLS

• Tools: Cadence Virtuoso, Spectre, Xilinx Vivado, ModelSim, ADS, Synopsys-VCS, Verdi, XA, Primesim, Primewave

• Programming: Verilog, VHDL, SystemVerilog, UVM, UVM-RAL, Verilog-A/MS

• Analog Skills: Analog MOS transistor models, Current mirrors, Differential Amplifiers and Operational Amplifiers

• Protocols: Advanced Microcontroller Bus Architecture (AMBA) - Advanced eXtensible Interface (AXI) and Advanced Peripheral Bus (APB), Serial Peripheral Interface protocol (SPI) EXPERIENCE

Kyyba Inc 18 Mar 2024 – Present

Role: Test Engineer

• Conducted functional, electrical, and reliability testing of Abbott Alinity i medical diagnostic devices and PCB assemblies using automated test equipment, validating operation against design specifications

• Utilized digital multimeters, oscilloscopes, power supplies, and electrical test equipment to troubleshoot voltage, current, timing, and signal-integrity issues at the PCB level

• Performed continuity and insulation-resistance testing and verified power distribution and signal integrity to identify electrical faults and ensure reliable hardware operation

• Verified the digital controller at the RTL level by generating ADC-equivalent digital stimulus using SystemVerilog/UVM and checking the controller's outputs, timing, and protocol behavior

• Investigated hardware and digital-interface test failures through waveform analysis, root-cause debugging, and correlation of expected digital behavior with measured PCB signals, collaborating with design and manufacturing teams on corrective actions

• Verified power distribution and signal integrity across circuit boards to ensure stable device operation Synopsys Aug 2022 – Jan 2023

Role: Analog and Mixed Signal - Intern (Technical Engineering)

• Worked on projects that involve utilizing state of the art fastSPICE (XA), Primesim, Finesim and Mixed-Signal Verification tools for the verification of AMS designs

• Worked with Circuit Simulation and Mixed Signal Verification software R&D’s to benchmark the simulation performances of AMS designs using behavioral models, SystemVerilog Real Numbers and Nettypes

• Generated tutorial and documentation for Phase-Locked Loop (PLL) FSDB (Fast Signal Data Base) waveform generation in mixed-signal simulation

• Conducted performance benchmarking for SystemVerilog, SPICE and Verilog-AMS/Verilog-A models/blocks in the design

• Implemented functional coverage metrics and SystemVerilog assertions to improve verification completeness

• Identified and resolved interface mismatches between analog and digital domains. Performed code coverage analysis using VCS to ensure design verification completeness

Blueberry Semiconductors Pvt Ltd Apr 2019 – Aug 2021 Role: Design Verification Engineer

• Developed UVM-based verification environment to validate Memory controller IP (SDRAM controller), implementing drivers, monitors, and scoreboards to verify read/write transactions and protocol compliance

• Modelled SDRAM timing constraints (tRCD, tRP, tRAS, etc.) and ensured verification coverage of all critical timing paths. Verified a 16x128 DRAM both SystemVerilog and UVM environments

• Developed a complete UVM-based verification environment for an AXI slave interface and implemented SystemVerilog functional coverage, and used scoreboards for data integrity checks

• Debugged AXI protocol violations using waveform viewers and SystemVerilog assertions, ensuring correct handshake, ordering, and data integrity

• Utilized Verdi for waveform debugging, analyzing simulation failures, and improving debug efficiency

• Implemented UVM RAL models for register abstraction and verified APB register read/write operations for DUT configuration registers

ACADEMIC PROJECTS

Design of an array of computational units with shared register file using Verilog on Artix-7 FPGA May 2022

• Designed four quadrants with each having 16- ALU’s and each ALU in a quadrant can either use global or local data memory to access the data to compute and instruction memory to send Instructions to the CU

• Generated gate level schematic, debugged the verilog hardware design and synthesized the code on Artix-7 FPGA Tools Used: Xilinx Vivado and Modelsim

Design of a two-stage Operational Amplifier using CMOS Oct 2021

• The CMOS Two-Stage Operational amplifier was designed for high gain, better phase margin and lower power dissipation

• Power dissipation of 0.276 mW for a 1.8 V power supply, Output Swing Voltage Range (OSVR) of 0.59 V, Slew Rate of 20 V/us, Unity Gain Bandwidth of 30 MHz, CMRR of 58 dB, differential gain of 54 dB, Phase Margin 0f 60 degrees are obtained as a result of design

Tools Used: Cadence Virtuoso

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