| Resume alert | Resumes 61 - 70 of 182 |
Design Electrical Engineering
Los Angeles, CA
... FPGA Prototyping of Bi-Drectional Counter [Tools: QuestaSim, Quatus-II] [June 2017] • A digital counter is synthesized on Altera Cyclone IV FPGA board. • STA and delay optimization is performed on the design. • Obtained 100% code coverage on RTL. ... - 2017 Sep 18
... FPGA Prototyping of Bi-Drectional Counter [Tools: QuestaSim, Quatus-II] [June 2017] • A digital counter is synthesized on Altera Cyclone IV FPGA board. • STA and delay optimization is performed on the design. • Obtained 100% code coverage on RTL. ... - 2017 Sep 18
Verilog, VHDL, Python, C, C#, PL/SQL
Los Angeles, CA
... Node: 45nm Tomasulo Processor (32 bit) with Out of Order execution, In Order Completion Summer 2016 Designed a 32 bit Out of Order Execution and In Order Completion Tomasulo Processor in VHDL and implemented on Nexys 4 Artix7 FPGA board. Implemented ... - 2017 Sep 15
... Node: 45nm Tomasulo Processor (32 bit) with Out of Order execution, In Order Completion Summer 2016 Designed a 32 bit Out of Order Execution and In Order Completion Tomasulo Processor in VHDL and implemented on Nexys 4 Artix7 FPGA board. Implemented ... - 2017 Sep 15
Design Electrical Engineering
Los Angeles, CA
... Nexys 4 Artix7 FPGA board. Implemented Re-Order Buffer (ROB) for in order completion, Copy Free Check pointing (CFC) and Free Register List (FRL) for usage of Register Alias Table (RAT). Designed Branch Prediction Buffer (BPB), Return Address Stack ... - 2017 Aug 17
... Nexys 4 Artix7 FPGA board. Implemented Re-Order Buffer (ROB) for in order completion, Copy Free Check pointing (CFC) and Free Register List (FRL) for usage of Register Alias Table (RAT). Designed Branch Prediction Buffer (BPB), Return Address Stack ... - 2017 Aug 17
ASIC design verification engineer
Los Angeles, CA
... Tcl HDL – VHDL Verilog System Verilog RELEVANT COURSES Advanced VLSI design ASIC design Semiconductor devices Lab for DSP and FPGA Computer arithmetic algorithms Computer system architecture Advanced microprocessor systems PERSONAL DETAILS Vignesh ... - 2017 Aug 10
... Tcl HDL – VHDL Verilog System Verilog RELEVANT COURSES Advanced VLSI design ASIC design Semiconductor devices Lab for DSP and FPGA Computer arithmetic algorithms Computer system architecture Advanced microprocessor systems PERSONAL DETAILS Vignesh ... - 2017 Aug 10
Engineering Design
Fullerton, CA
... and Mumbai, Fullerton, Microprocessors, Microwave (INDIA RF/GPA: GPA: INDIA Mixed 78/Fullerton, 80/100 100 Engineering, Signal FPGA CA, IC design) design, USA RF engineering, GPA: Random 3.3 Signal VLSI Analysis, testing and communication design for ... - 2017 Aug 04
... and Mumbai, Fullerton, Microprocessors, Microwave (INDIA RF/GPA: GPA: INDIA Mixed 78/Fullerton, 80/100 100 Engineering, Signal FPGA CA, IC design) design, USA RF engineering, GPA: Random 3.3 Signal VLSI Analysis, testing and communication design for ... - 2017 Aug 04
Electrical Engineering Test
Pico Rivera, CA
... for various test setups •Documented and analyzed large sets of data for process improvement using ROOT, and Excel •Implemented FPGA to modify software system parameters (Voltage, current, bit rate, delays, test length, and number of bits) to improve ... - 2017 Jul 15
... for various test setups •Documented and analyzed large sets of data for process improvement using ROOT, and Excel •Implemented FPGA to modify software system parameters (Voltage, current, bit rate, delays, test length, and number of bits) to improve ... - 2017 Jul 15
Design Project
Placentia, CA, 92870
... Ram Meghe Institute of Technology & Research, Badnera, INDIA August 2010 – June 2014 Bachelor of Engineering in Electronics & Telecommunication, GPA: 3.48 Knowledge Areas Digital Systems design with FPGA CMOS VLSI Design Low Power Digital IC Design ... - 2017 Jun 24
... Ram Meghe Institute of Technology & Research, Badnera, INDIA August 2010 – June 2014 Bachelor of Engineering in Electronics & Telecommunication, GPA: 3.48 Knowledge Areas Digital Systems design with FPGA CMOS VLSI Design Low Power Digital IC Design ... - 2017 Jun 24
Electrical Engineering Web Developer
Alhambra, CA
... http://kai-lin-pokemon-api.herokuapp.com/, https://pack1199.us/ ● Tutor of electrical engineering field at Illinois Institute of Technology October, 2011 – May, 2013 ● Awarded first prize in Jiangsu Province CPLD/FPGA Circuit Design Contest in 2009 - 2017 Apr 06
... http://kai-lin-pokemon-api.herokuapp.com/, https://pack1199.us/ ● Tutor of electrical engineering field at Illinois Institute of Technology October, 2011 – May, 2013 ● Awarded first prize in Jiangsu Province CPLD/FPGA Circuit Design Contest in 2009 - 2017 Apr 06
Design Engineer State University
Los Angeles, CA
... 90274 • aczof2@r.postjobfree.com • Cell 310-***-**** Electronic Design Engineer / FPGA Designer / Software SUMMARY OF QUALIFICATIONS ** *ear’s experience in design of hardware, software, high speed FPGA design and test systems from concept to test. ... - 2017 Apr 05
... 90274 • aczof2@r.postjobfree.com • Cell 310-***-**** Electronic Design Engineer / FPGA Designer / Software SUMMARY OF QUALIFICATIONS ** *ear’s experience in design of hardware, software, high speed FPGA design and test systems from concept to test. ... - 2017 Apr 05
Engineer Electrical Engineering
Rancho Palos Verdes, CA
Jason Huang **** ***** ***** ***** Rancho Palos Verdes, CA 90275 310-***-**** aczj2b@r.postjobfree.com SKILLS SUMMARY Over 15 years of experience in Electrical Engineering application design and development Demonstrated expertise in FPGA/ASIC ... - 2017 Mar 29
Jason Huang **** ***** ***** ***** Rancho Palos Verdes, CA 90275 310-***-**** aczj2b@r.postjobfree.com SKILLS SUMMARY Over 15 years of experience in Electrical Engineering application design and development Demonstrated expertise in FPGA/ASIC ... - 2017 Mar 29