Abhinav Upadhyaya

Present Address - **** Yorba Linda Blvd, Apt 94 Fullerton, CA 92831, USA

Email: ac0zvq@r.postjobfree.com

Phone: 657-***-****

Career Objective

To work for an esteemed organization in challenging and highly productive environment with challenging job responsibilities, continued learning and growth while being resourceful and innovative where my expertise is best put to use.

Education

California State University Fullerton, Fullerton, CA Spring 2017

Master of Science in Electrical Engineering(Major : Computer Engineering), GPA: 3.33

Prof. Ram Meghe Institute of Technology & Research, Badnera, INDIA August 2010 – June 2014

Bachelor of Engineering in Electronics & Telecommunication, GPA: 3.48

Knowledge Areas

Digital Systems design with FPGA

CMOS VLSI Design

Low Power Digital IC Design

Robotics Fundamentals

Mixed-Signal IC Design

Micro-programming and Embedded Microprocessors

VLSI Testing and DFT

Professional Experience Summary

Saicon Technologies India Pvt. Ltd. January 2014 – August 2015

Role: Industrial Faculty trainer

Subjects: CMOS VLSI Design, Microprogramming and embedded microprocessors, VLSI Testing and DFT, C programming fundamentals and algorithms.

Software Tools & HDL (Hardware description Languages)

FPGA Implementation and Synthesis: XILINX VIVADO Design Suite 2015.3, XILINX ISE.

Mathematical & Simulation Tools: MATLAB, Simulink.

Physical CMOS layout: Microwind

VHDL/Verilog Simulator: ModelSim, GHDL, Xilinx Vivado.

SPICE Simulator and Schematic Editor: LTSpice

HDL’s: VHDL, Verilog HDL.

NetBeans IDE, HyperTerminal.

Software Programming Languages

C, C++

Core/Advance JAVA

Projects

Project : 4 bit Gray down Counter (CMOS)

Description : CMOS physical layout of 4 bit Gray down Counter was designed using the Microwind software. It was identified that all the design constraints and rules were met. The proposed design consists of 4 J-K FF’s connected together that converts 4 bit binary input to gray code and gives the correct simulation results.

Role & Responsibilities: Single handedly worked on the approach, developed and implemented the design.

Project : 4 bit Adder/Subtractor (CMOS)

Description : CMOS physical layout of 4 bit Adder/Subtractor was designed using the Microwind software. All the design constraints and rules were met. The design comprises of 4 full adder circuits cascaded together that can add or subtract a 4 bit binary input and gives the correct simulation results.

Role & Responsibilities: Worked on the methodology and implemented the design by myself.

Project : Asynchronous FIFO Memory design

Description : Asynchronous FIFO was designed and simulated using the Verilog HDL and simulated on Xilinx Vivado 2015.2 tool. It consists of 4 bit input memory that can read and write based on the status whether the memory is full or empty and is simulated and the simulation output results were verified.

Role & Responsibilities: Conceptually worked on the approach and implemented the design.

Project : Traffic Light Controller

Description : The Traffic Light Controller was designed using Verilog HDL and was implemented using NEXYS 4 FPGA. Here we are using 3 LED’s available on the board to represent the output. Push buttons are used to opt for select lines. This implementation of four junction traffic light controller can be directly applied in real time by employing more number of such circuits.

Role & Responsibilities: Individually wrote the code using Verilog HDL and implemented the design on FPGA board.

Project : Digital Alarm Clock

Description : A digital alarm clock was designed using Verilog HDL and implemented on NEXYS 4 FPGA. 7-Segment display was used to display the time of the real time clock and switches to control and reset the time.

Role & Responsibilities: Single handedly worked on the Verilog code and implemented on FPGA board.

Project : MEMS Accelerometer based Fall Detector -

Description : Designed a prototype which detects if a person falls accidentally and identified that it is low power, cost efficient design as compared to other conventional methods. It also traces the location of the person, which when needed can be used to provide immediate help to them.

Role & Responsibilities: Project Leader. Involved in design approach, involved in MEMS sensor concepts and working methodology, analysis of the detection if a person falls, preparation of the final project report.

Other Experiences

Prof. Ram Meghe Institute of Technology & Research, Badnera, INDIA August 2012-May 2013

Role - Coordinator

Assisted in the organization for power-lifting competition at the university level in the college of engineering and was responsible to select the participants for the competition by assisting the staff.

Person profile

Experienced in working with multi-cultural and geographically disparate group.

Hardworking & dedication to work. Good Team play Skills.

Honesty, sincerity and positive thinking.

Keen to learn and acquire new skills and knowledge, self-disciplined.

Enthusiasm for learning & adaptation for state of art technologies.

Work Authorization/Status: F1 - OPT (eligible for 3 years with OPT extension)

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