Vignesh Saravanan

ac1q5u@r.postjobfree.com

SOFTWARE SKILLS

EDA TOOLS –

Cadence Encounter

RTL compiler ultra

Cadence Virtuoso

Mentor graphics IC station

Mentor graphics Calibre

Leonardo Spectrum

Model sim

Synopsys primetime

Altera Quartus II

Xilinx ISE

Xilinx Vivado

OPERATING SYSTEM-

Linux, Windows

PROGRAMMING SKILLS

C & C++

Python

Tcl

HDL –

VHDL

Verilog

System Verilog

RELEVANT COURSES

Advanced VLSI design

ASIC design

Semiconductor devices

Lab for DSP and FPGA

Computer arithmetic algorithms

Computer system architecture

Advanced microprocessor systems

PERSONAL DETAILS

Vignesh Saravanan

Authorized to work

in the USA

862-***-****

ac1q5u@r.postjobfree.com

PROFESSIONAL SUMMARY

Solution-driven engineer looking to contribute to ASIC Design Verification by utilizing my knowledge of the subject and strong analytical skills; adept multi-tasker and team-player with enthusiasm for challenging tasks.

EDUCATION

New Jersey Institute of Technology May 2017

Master of Science in Electrical Engineering GPA= 3.3/4 Anna University, India May 2014

Bachelors in Electronics and Communication Engineering GPA= 3.0/4 PROFESSIONAL EXPERIENCE

National Institute of Electronics and Information Technology June 2016 – August2016

● Verification planning, built UVM verification environment

● Developed coverage metrics, wrote test bench using system verilog / UVM, reported and analyzed test results.

Indian Institute of Technology -Madras July 2014-July 2015

● Worked on RISC based 32-bit C-class processor design (aimed clock speed 250MHZ)

● Synthesized the design in 35nm technology using Encounter and performed static timing analysis

● Helped design RISC based 64-bit I-class processor design (aimed clock speed 1GHZ)

● Synthesized in 55nm technology, assisted in static timing analysis and floor planning

● Experience in Python / Tcl scripting

(For detailed specification of I and C class design - http://rise.cse.iitm.ac.in/shakti.html) SCHOLASTIC EXPERIENCE

● Design of high speed 4*4 barrel shifter, optimized the design for reliability

- Designed shifter circuit using transmission gate in CMOS technology

- Designed schematic and full custom layout in 180nm technology

- Performed Physical verification (DRC and LVS check) and post-layout parameter extraction

● FPGA based PCI bus design for low power devices

- Designed Master & Target blocks using FSM for detailed structure to minimize power consumption. Met timing parameters using top-down approach

- Simulated test benches for I/O read, memory and configuration write

● ASIC implementation of UART design in 45nm technology

- Implemented RTL design in Verilog HDL, used ASIC design flow for RTL to GDSII in 45nm Technology. Formal verification of the final design using Cadence Virtuoso

- Performed Logic synthesis, physical verification of the design and resolved setup and hold time issues (Primetime STA)

● Multi-channel parallel NAND flash memory controller architecture design

- Implemented using Verilog HDL in Xilinx ISE, delay was calculated using Synopsys primetime

- Functional simulation and performance testing on the RTL of memory controller

● Design of N*N multiplier using 4*2 AMM module

- Designed a pipelined architecture using Verilog in Behavioral modelling

- Calculated Critical path and false path delays

- Performed parasitic extraction, layout area estimation, timing and power analysis

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