| Resume alert | Resumes 81 - 90 of 182 |
Engineer Management
Los Angeles, CA
... AREAS OF EXCELLENCE: SCADA • DCS • FPGA Design • Signal Processing Orcale VirtualBox • Project Management • Client Management • Process Instrumentation Systems Advanced Control Systems • Signal Process Transducers• Network & Wireless systems ... - 2016 Aug 23
... AREAS OF EXCELLENCE: SCADA • DCS • FPGA Design • Signal Processing Orcale VirtualBox • Project Management • Client Management • Process Instrumentation Systems Advanced Control Systems • Signal Process Transducers• Network & Wireless systems ... - 2016 Aug 23
Technical Support Software Developer
Los Angeles, CA
... Our group consisting of 5 engineers used a Terasic DE2i 150 development FPGA board to create a Nintendo Entertainment System (NES) emulator https://drive.google.com/open?id=1EmoBYR12znOIZrlFYjST UtYdz7Cf6NOeaxwH8RVV_U ● Bluetooth controlled RC car ... - 2016 Jul 29
... Our group consisting of 5 engineers used a Terasic DE2i 150 development FPGA board to create a Nintendo Entertainment System (NES) emulator https://drive.google.com/open?id=1EmoBYR12znOIZrlFYjST UtYdz7Cf6NOeaxwH8RVV_U ● Bluetooth controlled RC car ... - 2016 Jul 29
Design Data
Los Angeles, CA
... Synthesized on Artix-7 FPGA and tested using different instruction streams and test benches. Language: VHDL June’15 – Aug ‘15 Interface lab: To understand the need for handshaking to communicate the data (2 -way and 4-way handshakes) using FIFOs, ... - 2016 Jul 08
... Synthesized on Artix-7 FPGA and tested using different instruction streams and test benches. Language: VHDL June’15 – Aug ‘15 Interface lab: To understand the need for handshaking to communicate the data (2 -way and 4-way handshakes) using FIFOs, ... - 2016 Jul 08
Developer Software
Pasadena, CA
... Awards and Achievements: Published a paper titled “Implementation of low power Frame Synchronizer and Code Group Detector for 3G Asynchronous WCDMA system on FPGA” at IJVSPA, Vol.2, Issue 5, Sep-Oct 2012. Secured many prizes in college level essay ... - 2016 Jun 16
... Awards and Achievements: Published a paper titled “Implementation of low power Frame Synchronizer and Code Group Detector for 3G Asynchronous WCDMA system on FPGA” at IJVSPA, Vol.2, Issue 5, Sep-Oct 2012. Secured many prizes in college level essay ... - 2016 Jun 16
Electrical Engineer Engineering
Glendale, CA
... vending machine on an FPGA using Xilinx ISE Created a business model for an innovative security device called “BeSecure” Developed C/C++ scripts for image processing, pathfinding, ciphering/deciphering, vending machine Experience Lab Assistant, Dr. ... - 2016 Jun 12
... vending machine on an FPGA using Xilinx ISE Created a business model for an innovative security device called “BeSecure” Developed C/C++ scripts for image processing, pathfinding, ciphering/deciphering, vending machine Experience Lab Assistant, Dr. ... - 2016 Jun 12
Design Electrical Engineering
Fullerton, CA
Chaitrasri Putter Linkedin: https://www.linkedin.com/in/chaitra-shree-6972225a Phone: 714-***-**** Email: acu4yz@r.postjobfree.com Objective: Looking for challenging opportunity in the field of FPGA/VLSI Designing and verification (Backend designer) ... - 2016 Jun 07
Chaitrasri Putter Linkedin: https://www.linkedin.com/in/chaitra-shree-6972225a Phone: 714-***-**** Email: acu4yz@r.postjobfree.com Objective: Looking for challenging opportunity in the field of FPGA/VLSI Designing and verification (Backend designer) ... - 2016 Jun 07
Design Project
Lakewood, CA
... Structural and behavioral Verilog design in Xilinx ISE and on Spartan3E FPGA Computer architecture, Interface design, and Communications design. - UART/USART, MIPS-based CPU, recreation of Pong. Matlab Chart data, simulate signals and systems. ... - 2016 May 14
... Structural and behavioral Verilog design in Xilinx ISE and on Spartan3E FPGA Computer architecture, Interface design, and Communications design. - UART/USART, MIPS-based CPU, recreation of Pong. Matlab Chart data, simulate signals and systems. ... - 2016 May 14
Engineer Design
Los Angeles, CA
... Synthesis - Synopsys Design Compiler Gate Level Simulation - NCSim FPGA tools - Xilinx ISE and Vivado, Altera Quartus II Place & Route - Cadence Encounter Programming Languages: Verilog, SystemVerilog, C++, C, VHDL. Educational Background M.S in ... - 2016 Apr 24
... Synthesis - Synopsys Design Compiler Gate Level Simulation - NCSim FPGA tools - Xilinx ISE and Vivado, Altera Quartus II Place & Route - Cadence Encounter Programming Languages: Verilog, SystemVerilog, C++, C, VHDL. Educational Background M.S in ... - 2016 Apr 24
Engineer State University
Los Angeles, CA
... GPA: 3.70 PROFESSIONAL EXPERIENCE Boston Scientific May 2015 – Aug 2015 Summer Research and Development Intern, ASIC and FPGA Team Design verification of different blocks such as timer blocks, watchdog block, interrupt vector block, pattern ... - 2016 Apr 04
... GPA: 3.70 PROFESSIONAL EXPERIENCE Boston Scientific May 2015 – Aug 2015 Summer Research and Development Intern, ASIC and FPGA Team Design verification of different blocks such as timer blocks, watchdog block, interrupt vector block, pattern ... - 2016 Apr 04
Engineering Project
Pasadena, CA
... PROJECTS: Under Graduate Project Title: DESIGN AND FPGA IMPLEMENTATION OF CHANNEL ESTIMATION METHOD AND MODULATION TECHNIQUE FOR MIMO SYSTEM Description In this project we propose a new design and implementation of an end to end MIMO system. ... - 2016 Mar 24
... PROJECTS: Under Graduate Project Title: DESIGN AND FPGA IMPLEMENTATION OF CHANNEL ESTIMATION METHOD AND MODULATION TECHNIQUE FOR MIMO SYSTEM Description In this project we propose a new design and implementation of an end to end MIMO system. ... - 2016 Mar 24