| Resume alert | Resumes 91 - 100 of 182 |
Java Developer Computer Engineering
Los Angeles, CA
... The chip was composed of an 8-bit microcontroller (PicoBlaze) and UART interface which was developed and tested using the Nexys 2 FPGA board. The software used was Xilinx ISE Design Suite 12.4. + Designed and implemented a simple traffic light ... - 2016 Feb 15
... The chip was composed of an 8-bit microcontroller (PicoBlaze) and UART interface which was developed and tested using the Nexys 2 FPGA board. The software used was Xilinx ISE Design Suite 12.4. + Designed and implemented a simple traffic light ... - 2016 Feb 15
Control Engineer
Long Beach, CA
... Interfaced small input output modules with National Instruments MyRIO FPGA kit using Lab view Software. Voice Over IP (VoIP) and Parameters Affecting the Quality of Service (April 2014) In depth research on VoIP and its application Analyzed the ... - 2015 Nov 27
... Interfaced small input output modules with National Instruments MyRIO FPGA kit using Lab view Software. Voice Over IP (VoIP) and Parameters Affecting the Quality of Service (April 2014) In depth research on VoIP and its application Analyzed the ... - 2015 Nov 27
FPGA ASIC Hardware Design Engineer
Los Angeles, CA
Drew Martin 212-***-**** acsifk@r.postjobfree.com EDUCATION: University of Massachusetts Dartmouth North Dartmouth, MA BSEE ASIC/FPGA TOOLS: DOORS, MKS, Cadence, Mentor, PCIe, PCI, SYSTEM VERILOG, VHDL, NCSIM, VERILOG-XL, TCL, SYNPLICITY Synplify, ... - 2015 Nov 18
Drew Martin 212-***-**** acsifk@r.postjobfree.com EDUCATION: University of Massachusetts Dartmouth North Dartmouth, MA BSEE ASIC/FPGA TOOLS: DOORS, MKS, Cadence, Mentor, PCIe, PCI, SYSTEM VERILOG, VHDL, NCSIM, VERILOG-XL, TCL, SYNPLICITY Synplify, ... - 2015 Nov 18
Design Engineer
Los Angeles, CA
... 3) RTL Design and Implementation of 32-bit CFC-based Tomasulo single-core processor in Xilinx Artix 7 FPGA July 2014 - Aug 2014 Designed 32-bit Tomasulo processor with a subset of MIPS32 ISA having IF stage with blocking cache, and 4-deep IFQ, 2 ... - 2015 Aug 19
... 3) RTL Design and Implementation of 32-bit CFC-based Tomasulo single-core processor in Xilinx Artix 7 FPGA July 2014 - Aug 2014 Designed 32-bit Tomasulo processor with a subset of MIPS32 ISA having IF stage with blocking cache, and 4-deep IFQ, 2 ... - 2015 Aug 19
Design Engineering
La Habra, CA
... Leading projects in developing System/PCB/ASIC/FPGA for various Digital/Mixed-Signal/Analog applications. ? Highly experienced and knowledgeable in defining Hardware architecture and partition at different levels. ? Extensive hand-on R&D experiences ... - 2015 May 15
... Leading projects in developing System/PCB/ASIC/FPGA for various Digital/Mixed-Signal/Analog applications. ? Highly experienced and knowledgeable in defining Hardware architecture and partition at different levels. ? Extensive hand-on R&D experiences ... - 2015 May 15
java developer
Rowland Heights, CA
... 2012 Complete in class lab of DSP/FPGA, get a basic knowledge of that and do the project of echo cancellation with LMS algorithm in Matlab/Simulink. Feb. 2011 Complete a timer circuit on bread board by implementing certain electronic components. Aug ... - 2015 Mar 26
... 2012 Complete in class lab of DSP/FPGA, get a basic knowledge of that and do the project of echo cancellation with LMS algorithm in Matlab/Simulink. Feb. 2011 Complete a timer circuit on bread board by implementing certain electronic components. Aug ... - 2015 Mar 26
Design Electrical Engineering
Los Angeles, CA, 90007
... Familiar with RTL design in FPGA and FPGA Prototyping. Education M.S Electrical Engineering, GPA: 3.43 Expected Graduation: Dec 2014 University of Southern California Core Courses: VLSI System Design (EE577A/EE577B) Digital System Design (EE560) ... - 2014 Sep 12
... Familiar with RTL design in FPGA and FPGA Prototyping. Education M.S Electrical Engineering, GPA: 3.43 Expected Graduation: Dec 2014 University of Southern California Core Courses: VLSI System Design (EE577A/EE577B) Digital System Design (EE560) ... - 2014 Sep 12
Mechanical Engineering Assistant
Los Angeles, CA
... Developed LabView FPGA and PC programs for the automated system. • Solved material complications due to working with Hydrochloric and Nitric Acid. • Lab Assistant, January 2012 – April 2012 Brigham Young University: Mechanical Engineering Materials ... - 2014 Jul 30
... Developed LabView FPGA and PC programs for the automated system. • Solved material complications due to working with Hydrochloric and Nitric Acid. • Lab Assistant, January 2012 – April 2012 Brigham Young University: Mechanical Engineering Materials ... - 2014 Jul 30
Engineer Design
Covina, CA
... of Circuits for Smart Houses with AVR Microcontroller Designed BPSK and QPSK transmitters and receivers circuits using FPGA-Xilinx SPARTAN 3E Designed a complete automatic system to control lightning, blinds management and HVAC system for smart ... - 2014 May 19
... of Circuits for Smart Houses with AVR Microcontroller Designed BPSK and QPSK transmitters and receivers circuits using FPGA-Xilinx SPARTAN 3E Designed a complete automatic system to control lightning, blinds management and HVAC system for smart ... - 2014 May 19
Engineer Manager
Encino, CA
... Seeking a project management and development lead position that utilizes my strong background in SoC, CPU, FPGA and high speed SerDes. EXPERIENCE: Western Digital, Irvine, CA. April/2011 - Oct/2013 Senior Principal Engineer/EE Project Lead EE ... - 2013 Nov 01
... Seeking a project management and development lead position that utilizes my strong background in SoC, CPU, FPGA and high speed SerDes. EXPERIENCE: Western Digital, Irvine, CA. April/2011 - Oct/2013 Senior Principal Engineer/EE Project Lead EE ... - 2013 Nov 01