Verilog, VHDL, Python, C, C#, PL/SQL

NAVYA PRAMOD

Los Angeles, CA ***** +1-213-***-**** ac2bpq@r.postjobfree.com

LinkedIn: www.linkedin.com/in/navyapramod

Seeking to obtain a position in Digital VLSI or Computer Architecture that will utilise my developed skills in electrical engineering and circuit design.

EDUCATION

Master of Science – University of Southern California GPA: 3.5 Major: Electrical Engineering

Bachelor of Engineering – The National Institute of Engineering GPA: 4.0 Major: Electrical and Electronics Engineering

RELEVANT COURSEWORK

VLSI System Design, Computer Systems Architecture, Diagnosis and Design of Reliable Digital Systems, Solid State Processing and IC Laboratory.

TECHNICAL SKILLS

Programming Languages: Verilog, VHDL, Python, C, C#, PL/SQL Applications and Tools: ModelSim, Cadence Virtuoso, Xilinx ISE, Prime Time, Design Compiler, Conformal, Synopsys, Cadence First Encounter, .Net, Lab Windows, Kiel

ACADEMIC PROJECTS

Chip Multiprocessor with Router Network, Interface Components and Pipelined Processors Spring 2017 Designed a 4 Core Multiprocessor system that communicates data to other Cores through a 4 node Ring Network. Network Interface Components (NIC) connects each processor with the corresponding Router. Performed RTL-Routing flow using Synopsys Design Compiler

(Synthesis), Prime Time (STA), NCSim (Functional and post synthesis simulation), Cadence Conformal(Logic Equivalence Check) and Cadence Encounter(Place & Route). Node: 45nm

Tomasulo Processor (32 bit) with Out of Order execution, In Order Completion Summer 2016 Designed a 32 bit Out of Order Execution and In Order Completion Tomasulo Processor in VHDL and implemented on Nexys 4 Artix7 FPGA board. Implemented Re-Order Buffer (ROB) for in order completion, Copy Free Check pointing (CFC) and Free Register List (FRL) for usage of Register Alias Table (RAT). Designed Branch Prediction Buffer (BPB), Return Address Stack (RAS) for speculative execution and Store Address Buffer (SAB) for memory disambiguation.

Full Custom Design of Pipelined Processor Fall 2016 Designed a 5 stage pipeline processor with 8*16 Register file, 16-bit ALU, 6 bit multiplier and 1024 bit SRAM in CADENCE Virtuoso. Goal was to minimize Area*Delay*Power. Python scripts were used for verification. ATPG and Fault Simulator Design in C Programming Fall 2016 Designed Deductive Fault Simulator and Automatic Test Pattern Generator for combinational circuits with a preprocessor that generates SSAF’s list and performs fault collapsing for Collapsed Fault List. ATPG is implemented using D-Algorithm to generate test vectors. These test vectors are given to the fault simulator to verify whether the test vectors would detect the faults in the circuit. 1KB SRAM Design in Cadence Virtuoso Fall 2016

Designed the schematic and layout of a 1024 bit SRAM in 200nm technology. The SRAM design consists of Row Decoder, Column Multiplexer, Pre Charging Circuitry, Sense Amplifiers and Output Registers. FIFO Design with Clock Domain Crossing Summer 2016 Implemented a 2 clock FIFO to solve the problem of clock domain crossing using both Pipelined and Flow-Through BRAMs in VHDL. A register based FIFO is used along so that the producer need not wait the delay until the data is consumed. The delay is caused due to the extra registers before and after the FIFO.

Fabrication of Integrated circuit from Wafer to Chip Fall 2017 Development from a Silicon Wafer with fabrication process like Ion implantation and testing the circuits for functionalities. WORK EXPERIENCE

Systems Engineer, Tata Consultancy Services Ltd., India Nov 2013 – Dec 2015

Designed, developed and managed Testing and Performance Engineering solutions for Rolls Royce

Designed and developed interactive user interface web pages. Unit testing of the developed web pages for PNC Financial Services. Languages: C#, MVC, Kendo UI

Tools: Team Foundation Server, SQL Server 2008, and Visual Studio 2013, VB.NET

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