Design Electrical Engineering

Sai Gautham Thoppa

Address: **** **** ***** ****, **, CA 90007. Ph:213-***-**** Email:ac2c0c@r.postjobfree.com LinkedIn:www.linkedin.com/in/saigautham EDUCATION

University of Southern California, Master of Science in Electrical Engineering (GPA: - 3.95/4.0) Graduation: May 2018 Coursework:

Diagnosis and Design of Reliable Digital Systems(EE658), System Verification (EE580), Computer System Architecture (EE557), VLSI System Design (EE577a & EE577b), MOS VLSI Circuit Design (EE477L), Computer System Organization (EE457). Osmania University, India, B.E in Electronics and Communications Engineering (CGPA: - 3.86/4.0) Graduated: May 2015 TECHNICAL SKILLS

• Languages : System Verilog, Verilog, C, C++, Python

• Tools : QuestaSim, Quartus II, Matlab, Cadence Virtuoso, HSpice

• Interests : Verification, Digital VLSI, Computer Architecture PROJECTS

Power Aware Verification with UPF [Tools: QuestaSim] [July 2017]

• Created an UPF file to describe power intention of a design with LFSR, counter, sequence detector and BCD converter.

• Created power domains with isolation and retention strategy with help of power switches. AXI Protocol Reference Model in C++ [July 2017]

• Implemented classes for Master, Slave, Arbiter and Interconnect with functions for transaction channels.

• Round-Robin arbitration for request made by threads is used.

• Created a 4 Master 4 slave communication model.

Verification of Synchronous FIFO - UVM implementation [Tools: QuestaSim] [June 2017]

• Verified a synchronous FIFO using UVM testbench.

• UVM environment is developed with test consisting of environment with scoreboard, coverage and agents.

• Sequencer is modified to send transactions to driver, output generated is read by monitor and sent to scoreboard for comparison. FPGA Prototyping of Bi-Drectional Counter [Tools: QuestaSim, Quatus-II] [June 2017]

• A digital counter is synthesized on Altera Cyclone IV FPGA board.

• STA and delay optimization is performed on the design.

• Obtained 100% code coverage on RTL.

Verification of Asynchronous FIFO – SytemVerilog [Tools: QuestaSim] [June 2017]

• Developed a class based test-bench with interface, driver, monitor and scoreboard.

• Generated random test data for functional testing and assertions were used. Design of Digital Neuron with Sigmoid Activation in Verilog [Tools: Modelsim] [May 2017]

• Implemented a neural node using the IEEE 754 floating point multiplier and addition units.

• Sigmoid Activation function is implemented using floating-point divider and adder units. Design of Pipelined Microprocessor using Hardware and Software Components [Tools: Cadence Virtuoso, Python] [Apr 2017]

• Designed a 5-stage pipelined processor with 8x16 Register File(RF), 16 - bit ALU, 5 - bit Multiplier, 512 bit SRAM.

• Python script is designed for IF and ID stage of a pipeline, to resolve any data dependencies, to emulate ID stage and for functionality check of the CPU.

• The design is optimized for power using data gating, clock gating and delay with logical effort. Design of a 512-Bit SRAM Memory cell [Tools: Cadence Virtuoso, Python] [Feb 2017]

• Designed schematic and layout of a 512 bit SRAM with two 256 bit banks, row decoder, Pre-charge, Read/Write circuitry and Sense amplifiers.

• Developed a python script for simulation and result verification of SRAM. EXPERIENCE

Embedded System Design Intern, Hacklab Innovations, India [Nov 2015 - Apr 2016]

• Developed an embedded product for real time tracking device for commercial applications on Single Board Computers and Wi-Fi as the medium.

ACHIEVEMENT

• Course Grader for EE577a: VLSI System Design Course under professor Dr. Pierluigi Nuzzo in Fall 2017.

• Received “Most Potentially Disruptive Idea Award” at USC Stevens Student Innovator Showcase 2016.

• Quarter Finalist in Texas Instruments Innovation Challenge India 2015.

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