Jason Huang

**** ***** ***** *****

Rancho Palos Verdes, CA 90275

310-***-****

aczj2b@r.postjobfree.com

SKILLS SUMMARY

Over 15 years of experience in Electrical Engineering application design and development

Demonstrated expertise in FPGA/ASIC architecture and implementation

Experienced in complex requirement analysis, decomposition and verification using DOORS

Highly skilled in simulation and test bench development

Excellent team player, cross-functional coordinator, detailed oriented team-organizer

Ability to perform on classified programs - previously obtained DoD Secret clearance

Highly proficient in: Synthesis, PrimeTime, Xilinx and Altera FPGAs, Lab Integration, SystemVerilog/C/Perl/assembly/Matlab, UART/1553/PCI/RS485/Ethernet, RTL (VHDL and Verilog), DFT_FastScan, Command and Data Handling system, Digital Signal Processing

PROFESSIONAL EXPERIENCE

Lockheed Martin, Syracuse, New York 03/2016 - Present

ASIC/FPGA Engineer

DAHI ASIC

Design and implement DAHI ASIC for wireless communication

Generate VHDL codes for up/down-sampling, complex FIR, (I)FFT, polyphase channelizer and halfband filter

Generate VHDL codes for digital mixer and NCO for the baseband signal

Generate VHDL codes using Simulink; verify HDL codes using cosimWizard within Simulink

RIB FPGA

Implement RIB (Radar Interface Board) FPGA for TPQ-53 Counter Fire Target Acquisition Radar

Capture the FPGA requirements in DOORs and generate the Firmware Design Document

Design the interfaces for UDP Ethernet (1000BaseBx,100BaseT,1000BaseT), ADC and UART

Route the message from Radar Control to the appropriate external interface (AES, MFA, ExRx)

Design the Dwell Command Functionality and the Time Processing for the GPS

Design and write VHDL codes for the interfaces between Ethernet, UART, Flash Memory and DDR3

Synthesize, place and route, and implement the FPGA in Artix 7 FPGA using Vivado (2016) tool

Schneider-Electric, Lake Forest, California 06/2015 – 03/2016

Senior FPGA Engineer

Implement Digital Input FPGA for Trilogy Project using Xilinx Spartan6 FPGA

Design and verify DAC Interface for TI DAC5311 and ADC Interface for TI ADS7953 with SPI Bus

Design and verify SOE (Sequence of Events) and FVD (Forced Value Diagnosis) logics

Conduct code review using Collaborator and TFS for all modules

Integrate, simulate and debug Software/FPGA images with Atmel processor in the lab

Advanced Bionics, Valencia, California 12/2010 – 06/2015

Senior ASIC/FPGA Engineer

SC90K ASIC/FPGA for Caguaro project - key component of the cochlear implant device

Designed SC90K digital block using register-based RTL coding style for low power chip

Utilized Leonardo to synthesize the VHDL code for 1- and 2-phase clocking schemes

Ran the recursive simulation at netlist level with SDF file

Wrote RTL codes (VHDL and Verilog) into Altera Cyclone IV E FPGA using Altera Quartus 12.0

Implemented LPT and RS232 (UART) interfaces with internal FIFOs for FPGA simulation

Implemented DFT for scan chains, generated test patterns and interfaced with fab foundry

Created and debugged test cases; generated test bench for regression test

Quadrature FM Receiver ASIC/FPGA for Pantera/Naida Project - used in cochlear implant device

Developed VHDL code with scan chain for quadrature receive demodulation, and performed simulations in Modelsim

Generated scan patterns using DFT FastScan and simulated the patterns in Modelsim

Developed Matlab code for quadrature frequency modulation and demodulation, and for verification of the RTL VHDL code

Generated constraint file for timing analysis using PrimeTime tool

SPD4 ASIC/FPGA for Pantera/Naida Project - key component of the cochlear implant device

Modified the telemetry between forward telemetry and receiving module; performed verification of the functions against requirements

Simulated post-scan Verilog netlist, generated and debugged test patterns (functional and TMU) for pre-bump wafer test

Parker Aerospace, Irvine, California 04/2010 – 10/2010

Hardware Engineer (contractor)

Command FPGA and Monitor FPGA for EMB project – developed for balancing the airplane

Developed VHDL code, executed Modelsim Simulation (RTL and Gate), generated test bench.

Integrated FPGA and software in the lab. Debug any issues between firmware and software. Designed RS485 Serial RX/TX Interface, NVM (Flash Memory) Interface and Cyclic Redundancy Code blocks.

Orbital Science Corp, Dulles, VA 01/2010 – 04/2010

Electrical Engineer (contractor)

Satellite Communications FPGA and Control FPGA development for Cygnus Avionics Box (COTS)

Performed verification of the Launch Vehicle UART, SRAM, Operand Bus, Watch Dog timer, 1553 RT, setup time and hold time for ADC, and local telemetry transferring functions.

Northrop Grumman Aerospace Systems/TRW, Redondo Beach, CA 2001 –2009

Senior Member of Technical Staff/Project Lead - Received Recognition Award for the successful completion of the Telemetry FPGA IDR3 and PDR

Telemetry FPGA (TLM FPGA, Actel RTAX200S FPGA)

Developed an Unit-level specification based on the FPGA requirements from the DOORS database; detailed I/O diagrams, block diagrams, circuit diagrams and timing diagrams for ESA, EXT, CCU, XBOX, PCI I/F (8-lane PCI Express), SRAM I/F Controller, and Local Bus blocks

Battery Discharged Unit (BDU) Project

Performed architecture trades for BDU digital part that includes DDC 1553 Interface chip (1553B IP core), Actel Rad Hard FPGA, Intersil DAC and ADC chips. Designed the C&DH protocol that applies OBC, 1553B IP, DIO FPGA and REA FPGA.

HAL ASIC Project (for AEHF Phased Array Antennae)

Developed Visual C++ codes in Visual Studio Environment for both CAT_SYNC and DFB blocks to validate the HAL ASIC. Created test plans, verification matrix and flysheets for CAT_SYNC and DFB. Reached 99% of VHDL Cover (TransEDA VNCover) for CAT_SYNC simulation.

MINT ASIC Project (for AEHF Phased Array Antennae)

Texas Instruments Inc., San Diego, CA 2000 - 2001

ASIC Design/Application Engineer - PRIMA ASIC (SONY PRIMA Project) (contractor)

Raytheon Missile Systems, Tucson, AZ 1999-2000

Hardware Engineer - CHAMP ASIC (AMRAAM Phase III Missile)

Real 3D Inc., Orlando, FL 1997-1999

ASIC Design Engineer - Cobra ASIC and Sega ASIC

EDUCATION

M.S., Electrical Engineering

California State University, San Jose, CA

B.S., Electrical Engineering and Computer Science

University of California, Berkeley, CA

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