SUMMARY An RF/Ambitious HARDWARE/Electrical ASIC/ POWER Engineer, circuit familiar design Fullerton, and and experienced testing CA, Mob: to work with +1-TUSHAR 714-all widespread major 801-ARJUN 7163, standards organization, RAUT Email: in traut@electrical interested csu.fullerton.engineering, to explore edu new looking technology. for full time opportunity in EDUCATION

University California Bachelor Government Associate Masters Coursework: IC design, in in in Microcontroller Electrical State of Electrical Electrical CMOS Polytechnic, Mumbai, University VLSI Engineering Engineering Engineering Mumbai, Design, and Mumbai, Fullerton, Microprocessors, Microwave (INDIA RF/GPA: GPA: INDIA Mixed 78/Fullerton, 80/100 100 Engineering, Signal FPGA CA, IC design) design, USA RF engineering, GPA: Random 3.3 Signal VLSI Analysis, testing and communication design for testability, theory, Advance Nano electronics, Mixed May May May signal 201*-****-**** WORK EXPERIENCE

California State University, Fullerton, Instructional Student Assistant Oct 2016 to May 2017

• • Showed Assisted lecture. Helped a the commitment professor the professor in for conducting undergraduate to monitoring lecture instructing the for class (Introduction performance. through full to microprocessor participation in and grading microcontroller, homework, quizzes, Engineering projects Analysis)etc., Participate in each Reliance Infocomm Limited, Navi Mumbai, RF Intern July 2014 to Jan 2015

• • test, Part Hands and of on team analyzing knowledge who responsible reports of using generated RF for test technical lab from equipment’s support OSS. Troubleshooted to ex. 4G power LTE network, supplies, spectrum Monitoring oscilloscope, issues by the adjusting spectrum performance direction analyzer, of Cellular of Antennas power radio meters, from network vector remote by network conducting location. analyzer drive TECHNICAL SKILLS

Programing Tools Lab OS Protocol: Development and Equipment’s: and Applications: IDE: languages: Platform: C, Cadence Windows, LTE, Oscilloscope, FPGA, C++SPI,, Arduino, VHDL, RS232, Virtuoso, Unix/Spectrum Verilog, CPLD, Linux, I2C, Micro IEEE Microcontrollers, Perl, iOS, and 802.wind, MS Python, Vector office-11, ADS, TCP/Network Assembly word, LTspice, IP ARM, Suite, EXCEL, Analyzer, language, PIC HSPICE, IEEE 802.Signal M-MATLAB, 15.Scripting generator, 4, SIP Eagle, Digital Electric Modulator, VLSI, Express frequency PCB, Synthesizer GHDL PROJECTS AND ACEDEMIC RESEARCHES

Case study report on RF front end receiver module

• Studied front end receiver modules blocks ex, LNA, mixture, filter, local oscillator, demodulator, Baseband filter, audio amplifier etc.

• Demonstrated the matching parameter by theoretical calculation using smith chart and later compared them with output generated by ADS.

• Understand the theory of S parameter (S11, S22, S12, S21), transmission line (Micro-strip, CPW) and smith chart (Z-Y). Design of CMOS inverter using Cadence Virtuoso tool with GPDK 45nm technology.

• Design included PMOS NMOS with proper sizing ratio, consider all of breakdown, tradeoff, analyzed output waveform also calculated noise margin Analog CMOS Integrated Circuit design and Fabrication Process case study

• • Described Studied methodology the power management to design CMOS issue, circuit, effects Its of fabrication scaling on process performance, discuss way of optimum IC design at small device sizes Designing of ultra-low noise power supply for Analog Circuits

• For stable power supply to circuit we used buck or boost, SMPS (DC to DC) to produce rail voltage followed by linear regulator to reduce the noise

• Studied new approach to produce rail voltage DC to DC switching converter and LDO having good PSRR Design the layout of 4bit Adder/Subtractor using Micro wind VLSI IDE

• Designed and tested IC layout of Adder/subtractor circuit, verified the results, observed the delay by varying W/L ratio, layers and contact sizes.

• Anomaly Designed Detection prototype of Adulteration model, used principle Using Optoelectronics of laser science and optics, significant use of ADC, microcontrollers, PCB design and C programming Design and testing of ASIC SoC using self-activated auxiliary circuit (Term paper)

• Applied the theory of VLSI testing, Built in Test(BIST), design for testability, Boundary Scan architecture also memory and delay test

• Prepared block diagram of automated self-testing which may able to test chip and detect the error. High-Tech Production System

• Built a Prototype model for project, project is based of RTCC, used 8051 as development platform along with ADC, DAC, LCD display etc.

• Designed the PCB LAYOUT using eagle, etching of PCB, drilling, mounting, soldering of components, testing and troubleshooting. HONOURS AND AWARDS

• • Won Certified 2017 course “Outstanding on RF fundamental, Engineering Basic Student Concepts Award” and Components from Orange by County Rahsoft Engineering Irvine California Council. 2017.