Design Engineer State University

Kim Guzzino

*** *** ****** • Palos Verdes Estates, CA. 90274 • ********@*****.*** • Cell 310-***-****

Electronic Design Engineer / FPGA Designer / Software

SUMMARY OF QUALIFICATIONS

** *ear’s experience in design of hardware, software, high speed FPGA design and test systems from concept to test. Experienced in troubleshooting both in production and development environments.

Active participant in multiple IR&D and Ground Station development programs.

Technical Development positions of increasing responsibility and complexity from 1983 to present.

ACTIVE AREAS OF EXPERTISE

PATENTS AND AWARDS

Software

Design Tools/Platforms

TRW IR&D Honor Roll: VHSIC Electronics for

Advanced Signal Processing 1995 & 1996

Patent for Color Subcarrier Digital Phase Error

Detector 1997

TRW Chairman’s Award for High Speed Modem 1999

Python C VHDL

Visual Basic

Visual Studio

LabView Spice

Assembly Language

Xilinx, Actel, Altera, Unix/Linux/Windows

VME-VXI-PCI-1553- TCPIP

Mentor:Modelsim,D Architect

Cadence: Allegro, Orcad

Matlab/Simulink

Research Corporation of the University of Hawai’i Jan 2015 –Present(Contractor)

Recommend troubleshooting strategies and tests to operate a new 7 antenna correlator for the Yuan T Lee Array on Mauna Loa, Hi. Continue FPGA work to enhance the digital correlator functionality.

Academia Sinica Institute of Astronomy and Astrophysics – 2014-2015 (Contractor)

Developed a 10Gsps ADC board to attach to a UC Berkeley CASPER Roach2 board.

PCB design, layout and test with calibration software.

Assisted in the development of a packetized correlator for use on Yuan T. Lee Array, Mauna Loa Hi.

Research Corporation of the University of Hawai’i Jan 2011 –2014 (Contractor)

Review and advise development for an 18GHz bandwidth Radio Telescope Array

Study existing designs and provided FPGA expertise for a new ADC and board design.

Simulations and development using Matlab/Simulink, CASPER Library toolflow and Xilinx System Generator/ISE/EDK tools. Developed High speed LVDS interface block that is used by the Casper Astronomy community for all interfaces to the 5Gsps ASIAA ADC board.

Northrop Grumman Aerospace Systems (Formerly TRW Space and Technology) 1983 - 2010

IR&D Team / Ground Station Development:

Carrier Recovery IR&D

Developed the architecture, analyzed simulations and designed the board and FPGA for a Decision Directed PLL at 200Msps. Using Mentor Design Architect for Schematic, Xilinx ISE and Modelsim for FPGA design verification including post place and route simulations.

Digital Data Combiner IR&D

Developed a multi tera-byte data acquisition system with post processing, playback and GUI. Performed system architecture, simulations and software. Then designed a real time (800Msps) data combiner in hardware. Did board and FPGA designs using Xilinx and Mentor tools. Developed control and post-processing software in C and LabView running under Windows XP on a VXI platform.

RDE for Test and Operational Ground Systems Department Digital processing section:

Satellite Ground Station Demodulator/Bit Synchronizer

RDE for developing VHDL coding and board designs for Carrier Recovery Board(FPGA based VXI board)/ Adaptive Equalizer Unit(TI 320 DSP board) / AtoD Converter Slice(High Speed 3.2Gsps VXI Board) and High Speed Demux unit(Custom drawer).

Space Vehicle Simulator for Payload Testing

Architecture and high level design of a communication satellite payload test system including payload power control, load analysis, failure mode analysis, command and telemetry(1553 bus) interfaces, data logging and test sequencing using LabWindows and Labview, Ethernet, GPIB and custom interfaces.

Time Code Generator Test Unit

Designed a Time Of Day testing drawer with IRIG-B input and embedded PC104 processor. Ethernet and RS-232 interfaces, FPGA interfaces, wrote all FPGA code and test benches. Wrote requirements vs capability tables and verification matrix.

Software Experience

Northrop Grumman

Implemented TCP/IP code for remote control of an Adaptive Equalizer in a high data rate modem in C. Developed a data acquisition system with post-processing, playback and GUI in C.

Education: Ohio State University 1969

USAF 1971-75

Lowry AFB Co.: electronics, transistor theory, computer systems, communications, flight control, RADAR and armament control systems.

Publications/ A 5 Giga Samples Per Second 8-Bit Analog to Digital Printed Circuit Board for Radio Presentations: Astronomy" PASP: 126(942), 761-768, Sept 2014

The design of a10-Gsps analog-to-digital converter board for the radio astronomy community Conference: 2014 IEEE 23rd International Symposium on Industrial Electronics (ISIE)

A 4-Bit, 5Gsps ADC board for the radio astronomy community

Conference May 2013 ISIE

Digitizing The Yuan Tseh Lee Array for Microwave Background Anisotropy by 5Gsp ADC boards 978-1-4673-1260-8/12 IEEE Dec 2012

The Application of a Hierarchical Top-Down Parameterized VHDL Design Methodology to a Carrier Recovery Loop Filter ASIC Proceedings of the 1996 VHDL International Users Forum Durham, Oct. 27-30, 1996, pp.9

Digitizing AmiBA for CO Intensity Mapping

ASIAA 10 Gsps ADC Board Development

CASPER Workshop (Collaboration for Astronomy Signal Processing and Electronic

Research, UC Berkeley) NRAO Green Banks WV. 2012

The SMA/ASIAA 10 Gsps ADC board

CASPER Workshop GMRT Puni India 2011

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