Design Electrical Engineering

ACADEMIC QUALIFICATIONS

Designed, developed and managed Testing and Performance Engineering solutions for Rolls Royce

Designed and developed an electronic flow meter that incorporates flow control mechanism in a closed loop configuration and regulation for high operational efficiency of medical devices. Nexys 4 Artix7 FPGA board. Implemented Re-Order Buffer (ROB) for in order completion, Copy Free Check pointing (CFC) and Free Register List (FRL) for usage of Register Alias Table (RAT). Designed Branch Prediction Buffer (BPB), Return Address Stack (RAS) for speculative execution and Store Address Buffer (SAB) for memory disambiguation.

ATPG and Fault Simulator Design in C Programming Aug’16 Designed Deductive Fault Simulator and Automatic Test Pattern Generator for combinational circuits with a preprocessor that generates SSAF’s list and performs fault collapsing for Collapsed Fault List. ATPG is implemented using D-Algorithm to generate test vectors. These test vectors are given to the fault simulator to verify whether the test vectors would detect the faults in the circuit.

FIFO Design with Clock Domain Crossing. Jun’16

Implemented a 2 clock FIFO to solve the problem of clock domain crossing using both Pipelined and Flow-Through BRAMs in VHDL. A register based FIFO is used along so that the producer need not wait the delay until the data is consumed. The delay is caused due to the extra registers before and after the FIFO.

1KB SRAM Design in Cadence Virtuoso. Jun’16

Designed the schematic and layout of a 1024 bit SRAM in 200nm technology. The SRAM design consists of Row Decoder, Column Multiplexer, Pre Charging Circuitry, Sense Amplifiers and Output Registers.

Designed and developed interactive user interface web pages. Unit testing of the developed web pages for PNC Financial Services.

Languages: C#, MVC, Kendo UI Tools: Team Foundation Server, SQL Server 2008, and Visual Studio 2013, VB.NET Project Intern, Skanray Healthcare, India Sep 2012 - May 2013 University of Southern California, Los Angeles 2016 - Present Master of Science - Electrical Engineering

Relevant Courses: Computer Systems Organization, MOS VLSI Circuit Design, VLSI System Design I, Digital System Design

- Tools and Techniques, VLSI System Design II, Diagnosis and Design of Reliable Digital Systems. The National Institute of Engineering, Mysore, India 2009 - 2013 Bachelor of Engineering, Electrical and Electronics NAVYA PRAMOD Email: ac1vqe@r.postjobfree.com

742 West, 27th Street, Apt #34, Los Angeles, CA – 90007 Phone: 213-***-**** ACADEMIC PROJECTS

TECHNICAL SKILLS

Programming Languages: C, Verilog, PL/SQL, C#,VHDL, Python Applications and Tools: .Net, Modelsim, Cadence Virtuoso, Xilinx ISE, Lab Windows, Kiel, Prime Time, Design Compiler, Conformal, Synopsys, Cadence First Encounter

Full Custom Design of pipelined processor. Oct’16 Designed a 5 stage pipeline processor with 8*16 Register file, 16-bit ALU, 6 bit multiplier and 1024 bit SRAM in CADENCE Virtuoso. Goal was to minimize Area*Delay*Power. Python scripts were used for verification. Traffic Light Controller Feb’17

All the above are implemented and tested using Verilog. Performed Synthesis using Design Compiler on 180nm technology node and Gate Level Simulation in NC Sim.

Tomasulo Processor (32 bit) with Out of Order execution, In Order Completion Nov‘16 Designed a 32 bit Out of Order Execution and In Order Completion Tomasulo Processor in VHDL and implemented on WORK EXPERIENCE

Systems Engineer, Tata Consultancy Services Ltd., India Nov 2013 – Dec 2015

Chip Multiprocessor with Router Network, Interface Components and Pipelined Processors Mar’ 17 Designed a 4 Core Multiprocessor system that communicates data to other Cores through a 4 node Ring Network. Network Interface Components (NIC) connects each processor with the corresponding Router. Performed RTL-Routing flow using Synopsys Design Compiler(Synthesis), Prime Time(STA), NCSim(Functional and post synthesis simulation), Cadence Conformal(Logic Equivalence Check) and Cadence Encounter(Place & Route). Node: 45nm

Designs of Carry Save Multiplier, Pipelined ALU and Finite State Machines Controllers for a Vending Machine

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