| Resume alert | Resumes 61 - 70 of 77 |
Project Objective
Bangalore, KA, India
... : 17 Frequency : 200MHz Utilization : 69.5 % Technology/Layers : TSMC 0.13 micron/5 Metal Layers Page 1 of 3 Role: To perform sanity check, Floor Plan, Power Plan, Placement, Trail Route, Timing analysis, IPO, CTS, Detail Routing, RC extract, STA. ... - 2014 Jan 17
... : 17 Frequency : 200MHz Utilization : 69.5 % Technology/Layers : TSMC 0.13 micron/5 Metal Layers Page 1 of 3 Role: To perform sanity check, Floor Plan, Power Plan, Placement, Trail Route, Timing analysis, IPO, CTS, Detail Routing, RC extract, STA. ... - 2014 Jan 17
Validation engineer
Bangalore, KA, India
... • Undergone training in Advance Digital Designing, Synthesis, STA, FPGA Architecture, TCL scripting, Verification modules. • Experienced in system verilog for creation of verification environment using OOPS Concepts. EDUCATIONAL QUALIFICATION • Post ... - 2013 Dec 18
... • Undergone training in Advance Digital Designing, Synthesis, STA, FPGA Architecture, TCL scripting, Verification modules. • Experienced in system verilog for creation of verification environment using OOPS Concepts. EDUCATIONAL QUALIFICATION • Post ... - 2013 Dec 18
Quality Assurance Associate
Bangalore, KA, India
GAYATHRI THOMALA Mobile: +91-988******* Email: acat17@r.postjobfree.com OBJECTIVE Aiming to be associated with an esteemed organisation where I can utilize my skills and can contribute my best towards the organization objectives and to grow in the... - 2013 Nov 09
GAYATHRI THOMALA Mobile: +91-988******* Email: acat17@r.postjobfree.com OBJECTIVE Aiming to be associated with an esteemed organisation where I can utilize my skills and can contribute my best towards the organization objectives and to grow in the... - 2013 Nov 09
Project Design
Bangalore, KA, India
... Static Timing Analysis (STA). SLF. DRC and LVS checking. Device Physics. CMOS Logic Design. Cell Library Design and characterization. Testing and Verification. Worked on 16-bit Full adder Design. Tools Used Under Training: Modelsim VCS Concorde ... - 2013 Oct 08
... Static Timing Analysis (STA). SLF. DRC and LVS checking. Device Physics. CMOS Logic Design. Cell Library Design and characterization. Testing and Verification. Worked on 16-bit Full adder Design. Tools Used Under Training: Modelsim VCS Concorde ... - 2013 Oct 08
Engineer Design
Bangalore, KA, 560036, India
... Worked in all phases of ASIC design(P&R, STA, and Power Analysis) . Working in LSI India R&D Pvt. Ltd, Bangalore since December 2009 as a Senior Design Engineer. . Worked in ARM, Bangalore from December 2006 to December 2009 as a Design Engineer. . ... - 2013 Jun 24
... Worked in all phases of ASIC design(P&R, STA, and Power Analysis) . Working in LSI India R&D Pvt. Ltd, Bangalore since December 2009 as a Senior Design Engineer. . Worked in ARM, Bangalore from December 2006 to December 2009 as a Design Engineer. . ... - 2013 Jun 24
Design Engineer Project
Banglore, KA, India
... Digital design, memories, RTL, STA, validation of the timing reports, SI analysis, Physical design, Synthesis, Equivalence checks, Physical verification. . DFT scan stitching and scan insertion. . Hands on experience tools: Icc compiler, DC-Turbo ... - 2013 Jun 23
... Digital design, memories, RTL, STA, validation of the timing reports, SI analysis, Physical design, Synthesis, Equivalence checks, Physical verification. . DFT scan stitching and scan insertion. . Hands on experience tools: Icc compiler, DC-Turbo ... - 2013 Jun 23
Engineer Software
Bangalore, KA, 560078, India
... Technical Skill Set OpenLinK Endur : Open JVS, Open Component, Configuration on STA(Settlement & Accounting) Java Technologies : Java Swing, Servlet, JDBC, JSP and EJB Application & Web Servers : Jboss 3.2.6, Tomcat 6.0, Weblogic 8.1, Weblogic 9.2.3 ... - 2013 Apr 24
... Technical Skill Set OpenLinK Endur : Open JVS, Open Component, Configuration on STA(Settlement & Accounting) Java Technologies : Java Swing, Servlet, JDBC, JSP and EJB Application & Web Servers : Jboss 3.2.6, Tomcat 6.0, Weblogic 8.1, Weblogic 9.2.3 ... - 2013 Apr 24
Design Data
Bangalore, KA, 560029, India
... Good Working Knowledge of DESIGN SYNTHESIS and STA (SYNOPSYS-DC, PT- SHELL). . Knowledge of complete ASIC FLOW (RTL TO GDSII) and PROCESS DESIGN KIT (PDK). . Built inflow in VERILOG HDL and TCL/PERL SCRIPTING LANGUAGE. Accomplishments . Merit ... - 2013 Apr 13
... Good Working Knowledge of DESIGN SYNTHESIS and STA (SYNOPSYS-DC, PT- SHELL). . Knowledge of complete ASIC FLOW (RTL TO GDSII) and PROCESS DESIGN KIT (PDK). . Built inflow in VERILOG HDL and TCL/PERL SCRIPTING LANGUAGE. Accomplishments . Merit ... - 2013 Apr 13
Design Engineer
Bangalore, KA, India
... - My expertise lies in handling physical design blocks for Synthesis, placement and routing, CTS, FEV, STA, ECO implementations, power analysis and Physical verification using the industry standard tools like: DC-compiler (DC-T), IC-Compiler, Prime ... - 2013 Mar 25
... - My expertise lies in handling physical design blocks for Synthesis, placement and routing, CTS, FEV, STA, ECO implementations, power analysis and Physical verification using the industry standard tools like: DC-compiler (DC-T), IC-Compiler, Prime ... - 2013 Mar 25
perl,layouts,physical design,verilog,system verilog
banglore, KA, India
... PROFESSIONAL PROFILE -Completed training as a trainee engineer in IIVDT for a duration of six months in Physical Design, Synthesis and STA of ICs using Cadence tool(ENCOUNTER) as Physical Design Engineer and in Verilog & Verification using Cadence ... - 2013 Mar 14
... PROFESSIONAL PROFILE -Completed training as a trainee engineer in IIVDT for a duration of six months in Physical Design, Synthesis and STA of ICs using Cadence tool(ENCOUNTER) as Physical Design Engineer and in Verilog & Verification using Cadence ... - 2013 Mar 14