Appala Anil

Mobile: +917********* Email:

abrkos@r.postjobfree.com

Career Focus

To pursue a challenging career in VLSI Industry where I can apply my

creative skills and could be towards advancement of the organizational

objectives.

Education and Training

RV-VLSI Design Center, Bangalore, 2012-13.

ADAD -Advanced Diploma in ASIC (Application Specific Integrated Circuits)

Design.

JNTU-H/ Jyothishmathi Institute of Technological Sciences, 2012

B.TECH Electronics and Communication

77.0%

Jawahar Navodaya Vidyalaya, 2007

10+2 MPC (CBSE) 75.4%

Jawahar Navodaya Vidyalaya, 2005

10th CBSE 90.0%

Technical Skills

. Appreciable content on various DIGITAL STANDARD CELL LIBRARY design

concepts.

. Strong Hold regarding entire NUANCES IN SUBMICRON REGIME (STI): STRESS

effects WPE, LOD and DEVICE ISOLATION TECHNIQUES (TRIPLE

NWELL).Critical Dimension, Density rules, ANTENNA DIODE and

ELECTROMIGRATION.

. Solid practice on ELDO SIMULATOR for CHARACTERIZATION of standard

cells.

. Hands-on Experience with EDA tools like MENTOR GRAPHICS SPICE DESIGN

ARCHITECT, IC-STUDIO AND IC-STATION TOOLS for

LAYOUT/SPICE/LVS/DRC/DFM.

. Good fundamental understanding of ANLOG CMOS basics, LAYOUT

concepts and methods for ANALOG and DIGITAL STANDARD CELLS and MEMORY

CELLS.

. Possess expertise in DIGITAL CIRCUIT and LOGIC DESIGN.

. Good Working Knowledge of DESIGN SYNTHESIS and STA (SYNOPSYS-DC, PT-

SHELL).

. Knowledge of complete ASIC FLOW (RTL TO GDSII) and PROCESS DESIGN KIT

(PDK).

. Built inflow in VERILOG HDL and TCL/PERL SCRIPTING LANGUAGE.

Accomplishments

. Merit Scholarship Certificate for academic excellence in South India

Level 10th CBSE.

. Awarded Gold medal for academic excellence in 10+2 from IAS officer.

. Only student from Hyderabad Zonal region to participate in National

Level Children Science Congress held at IISC, Bangalore in 2006.

. Active participation in Physics Regional Level Exhibition Meet in

2006.

. Active participation in the Anti-Corruption Movement organized by

Youth for Better India

Projects

1) Design and characterization of 90nm and 180nm technology standard

cells.

Design and Characterization of 90 nm and 180 nm combinational and

sequential standard cells like NOT, NOR, NAND, OR, AND, HALF-ADDER,MUX

and DFLIP-FLOP with different drive strengths (range from 1X to 20X) and

verification process of standard cells by DRC, LVS and PEX.

Challenges Undertaken:

. Deciding the width of NMOS and PMOS transistors to meet the

standard cell size, the issues of standard cells size is resolved

by Transistor finger/folding technique.

. The smart ground work for efficient floor plan of layout design in

order to degrade the parasitic involved with Active and Polysilicon

by aligning them with minimum extensions over design.

Tool used: IC studio, IC station (mentor graphics) and Calibre

(drc, lvs, pex)

2) Design of various analog circuit layouts in 90nm technology.

Designed various analog circuits like current mirrors, differential

amplifiers and two stage operational amplifiers.

Challenges Undertaken:

. Developing efficient floor plan for proper placement of various

blocks.

. Strictly adhering to device, resister, and capacitor matching

techniques.

. Sitting of guard rings around active transistors and following

transistor fingers.

Tool used: IC studio, IC station (mentor graphics) and Calibre

(drc, lvs, pex)

3) Block-level physical design of I2C.

Aim: To understand the entire PD-FLOW and resolving various errors

highlighted in the design of i2c block-level implementation.

Challenges Undertaken:

Understanding of the inputs and outputs of all the stages in the

physical design (Floor Planning, Placement, CTS, Physical Routing

and DFM). Analyzing timing violations and fixing them at every stage &

fixing the errors or issue at every stage of flow.

Tool used: ICC-SHELL (Synopsys)

4) Image processing chip, block level design 32 macro_150k logic 180

nm.

Challenges Undertaken:

. Understanding Synopsys reference methodology.

. Understanding data flow diagram and design specifications.

. Understanding the parameters of technology and library files.

. Setting up the ICC design variables.

. Implementing DFT aware flow for design planning.

. Understanding issues related to multi-voltage cells.

. Understanding design and timing constraints of the design.

. Implementing inter clock aware design flow.

. Applying concepts of timing de-rate factors for a pessimistic timing.

. Understanding the concepts related to route guide.

. Grouping logic related to a block together in the design.

. Understanding issues related to macro placement like macro stacking,pin

Orientation, flip and defining minimum area constraints to avoid

DRC errors.

. Placement of macros based on data transfer between ports and

associated logic, resolving floating shapes and floating pin errors,

IR drop analysis.

. Understanding issues related to macro placement like macro stacking,pin

Orientation, flip and defining minimum area constraints to avoid

DRC errors.

. Standard cell Placement, analyzing timing reports, reporting paths

which are not fixable in physical design flow and set up time

closure.

. Defining CTS parameters like NDR, CTS, Post CTS optimization and hold

time closure.

. Routing and post routing optimization of block which included

challenges like iterating design flow to close timing and DFM.

. Performing post routing STA, DRC and LVS.

Tool used: ICC-SHELL (Synopsys)

5) 8 bit Synthesizable ALU Design and Development of self-checking File

input - File output test bench architecture.

Design of 8 bit ALU which performs arithmetic and logical operations on

the data and command inputs read from a file. Verification architecture

performs quantitative analysis and reports results into a file.

Tool used: Questa Sim (Mentor Graphics)

6) Synthesizable FIFO Design using SRAM and Development of self-checking

File input - File output test bench architecture.

FIFO design using SRAM soft IP which included challenges like

synchronizing FIFO depth with respect two different clocks. Verification

included feature extraction and quantitative analysis, which is reported

in a file.

Tool used: Questa Sim (Mentor Graphics)

Personal Strengths

. Self-motivated and hard-worker.

. Willingness to walk extra mile to achieve excellence.

. Acquaintance of Leadership skills.

Personal Profile

Name : Appala Anil

Father Name. : Komuraiah

Gender : Male

Date of birth : 25-10-1989

Hobbies : Playing cricket, football and surfing for latest

technologies on the web

Languages : English, Hindi and Telugu

Declaration

I hereby declare that the above mentioned information is correct up to my

knowledge, and I bear the responsibility for the correctness of the above

mentioned particulars.

(Appala

Anil)

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