| Resume alert | Resumes 51 - 60 of 77 |
ASIC Design and Verification Engineer
Bangalore, KA, India
... • Clear concepts on DFT, STA, Physical Design, C-MOS Technology, Layout Design and Schematic Drawing • Knowledge on the Basics of Scripting language Perl. • Educational Background BOARD OF YEAR OF PERCENTAGE OF COURSE INSTITUTE EDUCATION PASSING ... - 2014 Aug 26
... • Clear concepts on DFT, STA, Physical Design, C-MOS Technology, Layout Design and Schematic Drawing • Knowledge on the Basics of Scripting language Perl. • Educational Background BOARD OF YEAR OF PERCENTAGE OF COURSE INSTITUTE EDUCATION PASSING ... - 2014 Aug 26
Project Design
Bangalore, KA, India
... NC Sim DFT RTL compiler Layout Encounter Physical Design STA > Indian Institute Of VLSI Design & Training - Bangalore, Karnataka Post Graduate Diploma in VLSI Design & Technology Six Month Full Time Course in VLSI Design based on Cadence flow. ... - 2014 Jul 26
... NC Sim DFT RTL compiler Layout Encounter Physical Design STA > Indian Institute Of VLSI Design & Training - Bangalore, Karnataka Post Graduate Diploma in VLSI Design & Technology Six Month Full Time Course in VLSI Design based on Cadence flow. ... - 2014 Jul 26
VLSI ASIC Physical design engineer
Bangalore, KA, India
... > RC extract, STA. > Started the Design with 70% utilization. Completed the initial pnr run to get the scaling factors. Building the CTS is critical. After CTS gets the Clock Gating setup timing violations & to fix those implemented the CTS with ... - 2014 Jul 14
... > RC extract, STA. > Started the Design with 70% utilization. Completed the initial pnr run to get the scaling factors. Building the CTS is critical. After CTS gets the Clock Gating setup timing violations & to fix those implemented the CTS with ... - 2014 Jul 14
Project Design
Bangalore, KA, India
... • Basic knowledge of Static Timing Analysis (STA). • Education : Institute Year of Degree Discipline Aggregate University Passing RV-VLSI Design PG Diploma VLSI 2014 Center Rajeev Gandhi College of Electronics & BE/B.Tech Engineering and 2013 71 % ... - 2014 Jun 23
... • Basic knowledge of Static Timing Analysis (STA). • Education : Institute Year of Degree Discipline Aggregate University Passing RV-VLSI Design PG Diploma VLSI 2014 Center Rajeev Gandhi College of Electronics & BE/B.Tech Engineering and 2013 71 % ... - 2014 Jun 23
High School Engineering
Bangalore, KA, India
... Good knowledge of STA and Signal integrity issues. Good knowledge of Physical Design flow. Project Profile. • Academic Projects. • M.Tech. Title : Efficient Reversible Low Power Multiplier using Vedic Mathematics for Image Applications. • B.E. Title ... - 2014 Apr 26
... Good knowledge of STA and Signal integrity issues. Good knowledge of Physical Design flow. Project Profile. • Academic Projects. • M.Tech. Title : Efficient Reversible Low Power Multiplier using Vedic Mathematics for Image Applications. • B.E. Title ... - 2014 Apr 26
Design Project
Bangalore, KA, India
... Well knowledge of PHYSICAL DESIGN flow in Floor planning, Power planning, Placement, Clock Tree Synthesis(CTS), Routing,Static Timing Analysis(STA), IR Drop Analysis and Crosstalk. . Good knowledge of Digital Design Concepts. . Good knowldge of CMOS ... - 2014 Apr 16
... Well knowledge of PHYSICAL DESIGN flow in Floor planning, Power planning, Placement, Clock Tree Synthesis(CTS), Routing,Static Timing Analysis(STA), IR Drop Analysis and Crosstalk. . Good knowledge of Digital Design Concepts. . Good knowldge of CMOS ... - 2014 Apr 16
M.Tech VLSI Fresher with Skills in Verilog,VHDL,System verilog,UVM,STA
Bangalore, KA, India
... Experience in Logic Design and STA. . Proficient in RTL design, simulation and synthesis using Xilinx ISE. . Strong testing and debugging skills. . Experience in developing TB and TB components for block level verification using system verilog. . ... - 2014 Apr 15
... Experience in Logic Design and STA. . Proficient in RTL design, simulation and synthesis using Xilinx ISE. . Strong testing and debugging skills. . Experience in developing TB and TB components for block level verification using system verilog. . ... - 2014 Apr 15
VLSI Engineer
Bangalore, KA, India
... Digital Electronics, Digital Circuit Design, Timing Analysis (STA and DTA), CMOS. SOFTWARE SKILLS . Verilog, VHDL, C language, Linux HANDS ON WORKING KNOWLEDGE . FPGA Architecture v4, v6, Questa Sim, Emacs, Xilinx ISE, Linux Shell Scripting, Micro ... - 2014 Apr 02
... Digital Electronics, Digital Circuit Design, Timing Analysis (STA and DTA), CMOS. SOFTWARE SKILLS . Verilog, VHDL, C language, Linux HANDS ON WORKING KNOWLEDGE . FPGA Architecture v4, v6, Questa Sim, Emacs, Xilinx ISE, Linux Shell Scripting, Micro ... - 2014 Apr 02
ASIC & Verification Trained/Verilog,System Verilog,UVM
Bangalore, KA, India
... Area of Interest : Digital Design, RTL Coding, STA, Digital Communication. Tools : Xilinx, Model Sim, Lab View. ACHIEVEMENTS . Secured 114th Rank in APRJC Exam. . Received "Sir Isaac Newton" prize in the academic year 2010-2011 for securing best ... - 2014 Apr 02
... Area of Interest : Digital Design, RTL Coding, STA, Digital Communication. Tools : Xilinx, Model Sim, Lab View. ACHIEVEMENTS . Secured 114th Rank in APRJC Exam. . Received "Sir Isaac Newton" prize in the academic year 2010-2011 for securing best ... - 2014 Apr 02
Design Project
Bangalore, KA, India
... • Knowledge of Verilog, STA, Synthesis, Floor planning, Placement, CTS, Routing, DFM. • Knowledge of DRC, LVS. • Knowledge of TCL,PERL. Education : Degree Discipline Institute University Year of Passing Aggregate PG Diploma VLSI(Physical Design) RV ... - 2014 Feb 25
... • Knowledge of Verilog, STA, Synthesis, Floor planning, Placement, CTS, Routing, DFM. • Knowledge of DRC, LVS. • Knowledge of TCL,PERL. Education : Degree Discipline Institute University Year of Passing Aggregate PG Diploma VLSI(Physical Design) RV ... - 2014 Feb 25