Engineer Design
Resume:
RESUME
E. SUDHAKAR
Maragondanahalli Main Road,
KR Puram,
Bangalore - 560036.
Email: ******.********@*****.***
Mobile: +91-991******
Objective
Commit myself for dedicated hard work to develop skills and acquire
knowledge to lead the organization towards new horizons of success, while
holding a responsible position in semiconductor industry.
Experience summary
. Worked in all phases of ASIC design(P&R, STA, and Power Analysis)
. Working in LSI India R&D Pvt. Ltd, Bangalore since December 2009 as a
Senior Design Engineer.
. Worked in ARM, Bangalore from December 2006 to December 2009 as a
Design Engineer.
. Worked in Cadence, Noida from June 2006 to December 2009 as a Trainee
Engineer.
Skill Set
. 7.1 years of full-time experience in VLSI industry.
. 3.7 years of Experience in P&R, Timing, and IR drop Analysis.
. Got Experience to the different stages of ASIC implementation flows
like, Floorplan, Powerplan, Placement, CTS, Routing, Extraction,
Timing Closure, and Power Analysis while working in different
projects.
. 3.6 years of experience in High Performance and High Density Standard
Cell Library development (Standard cells/Custom cells circuit design,
Optimization of cells for performance and area, Layout design of
Standard cell/Custom cells and Characterization)
. Good programming skills in PERL, TCL, and CShell
EDA Experience
Back-End Tools : IC-Compiler (ICC), Virtuoso
STA Tools : Primetime (PT)
IR drop Analysis : Apache (RedHawk)
Physical verification : Calibre
Simulations : SiliconSmart, HSpice
Extraction : StarXtract
Scripting Language : PERL, TCL, and CShell
Projects undertaken at LSI India R&D Pvt. Ltd
Physical Implementation of Cetus 28G SerDes 28nm chip
Duration: November 2012 to May 2013
Team Size: 5
Roles and responsibilities
. Block level Physical Design Implementation (right from constraint
collection, Floor Plan, till GDS).
. Block level Timing Closure for 8 corners and 2 modes (28G and 16G).
. Chip level Power Analysis (Static and Dynamic IR Drop analysis)
Design Challenges
. Floor Plan creation with less congestion and reduced area.
. Clock building with control fanout structures and better balancing.
. Timing Closure at 8 corners.
Physical Implementation of TC1218 Memory chip
Duration: July 2012 to November 2012
Team Size: 4
Roles and responsibilities
. Chip level Physical Design Implementation (right from constraint
collection, Floor Plan, till GDS).
. Chip level Power Analysis (Static and Dynamic IR Drop analysis).
Design Challenges
. Controlled placement of Standard cells at the Memory boundaries.
. Efficient Power grid creation to have less IR Drop in 3rd Quadrant
where memory placement is dense.
Physical Implementation of TC1217 Memory chip
Duration: March 2012 to July 2012
Team Size: 4
Roles and responsibilities
. Chip level Physical Design Implementation (right from constraint
collection, Floor Plan, till GDS).
. Chip level Power Analysis (Static and Dynamic IR Drop analysis).
Design Challenges
. Controlled placement of Standard cells at the Memory boundaries.
. Efficient Power grid creation to have less IR Drop in 2rd Quadrant
where memory placement is dense.
Physical Implementation of VLSRAM Memory 28nm chip
Duration: July 2011 to February 2012
Team Size: 4
Roles and responsibilities
. Chip level Physical Design Implementation (right from constraint
collection, Floor Plan, till GDS).
. Chip level Timing Closure for 6 corners.
Design Challenges
. Clock building and balancing.
. Timing closure at 6 corners.
. Completing the project in tight schedule.
Physical Implementation of SAGA 2.1G DDR3 28nm chip
Duration: November 2010 to June 2011
Team Size: 5
Roles and responsibilities
. Chip level Physical Design Implementation (right from constraint
collection, Floor Plan, till GDS).
. Chip level Power Analysis (Static and Dynamic IR Drop analysis)
Design Challenges
. Floor Plan, Clock building and balancing.
Physical Implementation of KIVA 1.6G DDR2/3 28nm chip
Duration: February 2010 to October 2010
Team Size: 5
Roles and responsibilities
. Chip level Physical Design Implementation (right from constraint
collection, Floor Plan, till GDS).
. Chip level Timing closure.
Design Challenges
. Floor Plan, Clock building and balancing.
. Timing closure at 6 corners.
Education Profile
. Completed M.Tech in Microelectronics and VLSI Design from IIITG.
. Completed B.Tech in Electronics and Communication Engineering from
J.N.T.U. University, Hyderabad.
Personnel Details
Date of Birth : 6th APR 1981
Sex : Male
Father's name : Elluri NagiReddy
Languages known : English, Hindi, Telugu
I hereby declare that all the statements made in this resume are true
and correct to the best of my knowledge and belief.
Place: Bangalore
Elluri Sudhakar
Date: 05/06/2013
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