CURRICULUM VITAE

KARTHIK CHANDRA PEDDI

Birth : 7th May 1991, India

Sex & Marital Status : Male, Single

Address: Thimma reddy building,1st main 3rd A cross

Malleshpalaya, New Tippasandra,Bangalore. Pin 560075.

Email : acb619@r.postjobfree.com

Mobile : +91-900*******

Objective:

Seeking a challenging job to work in a stimulating environment where I can apply & enhance my

knowledge, skill to achieve organizational goals and professional growth.

Professional Training:

An Industry Oriented Training in VLSI Physical Design from Institute of Silicon Systems Pvt. Ltd.,

Hyderabad since July 2012.

Course outline:

VLSI Fundamentals, CMOS Basics, Digital Design Floor Planning, Power Planning, Placement and

Routing, clock tree synthesis, static timing analysis timing optimization, cross talk analysis, IR Drop

Analysis and Physical Verification .

Tools:

Experience in physical design of 90nm, 130nm and 180nm technologies using Cadence tool

Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis

Encounter Timing System –Static Timing Analysis and Crosstalk Analysis

RTL - Logic Synthesis

Academic Education:

B-Tech in Electronics and Communications Engineering from The ICFAI University, Tripura

with an aggregate of 7.01 CGPA, 2012

Intermediate from Narayana Junior College, Visakhapatnam with an aggregate of 90%, 2008

Secondary Education J.M.J E.M High School, Anakapalli with an aggregate of 87%, 2006

PROJECTS:

Physical Design

Project 1: (Top Level)

Objective : Timing Driven Layout

Tools : SOC Encounter, QRC, ETS.

Gate count/Area : 296,296 / 1,508,801.9 um2

Macros /STD Cells : 12 / 25195

No. of Clocks : 17

Frequency : 200MHz

Utilization : 69.5 %

Technology/Layers : TSMC 0.13 micron/5 Metal Layers

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Role: To perform sanity check, Floor Plan, Power Plan, Placement, Trail Route, Timing

analysis, IPO, CTS, Detail Routing, RC extract, STA.

Project 2: (Top Level)

Objective : Timing Driven Layout

Tools : SOC Encounter, ETS.

128,961 / 1,572.915 um2

Gate count/Area :

Macros /STD Cells : 12 / 24,450

No. of Clocks : 4

Frequency : 149.9 MHz

Utilization : 52.1 %

Technology/Layers : TSMC 0.18 micron/5 Metal Layers

Role: To perform audit checks, Floor Plan, Power Plan, Placement, IPO, Trial Route, Timing

Analysis, CTS, Detail Routing. To achieve 0 % congestion at trial route stage

Project 3

Objective : To observe the usage of metal layers

Tools : SOC Encounter

7,701 / 76,856 um2

Gate count /Area :

STD Cells : 2477

No. of Clocks : 3

Frequency : 333 MHz

Utilization : 70.1 %

Technology / Layers : UMC 0.18 micron / 5 Metal Layers

Role: To perform audit checks, Floor Plan, Power Plan, Placement, IPO, Trial Route, Timing

Analysis, CTS, Detail Routing. To observe the relation between core utilization, wire length and

number of metal layers.

Logic Synthesis:

Project 1

Clocks : 2

Frequency : 200MHz

Role: Generated Constraint file, TCL file and Performed Wire load and Zero Wire load model.

Project 2

Role: Calculated the Clock Frequency, Generated Constraint file, TCL file, Performed Wire load

and Zero Wire load model.

Layouts:

Tool : Cadence Virtuoso

Design : Basic gates

Role: Designed Layouts for Basic gates like Inverter, Buffer, Nand, Nor, And, Or gates

Academic Projects:

Internship 1

Organization : Sygnovate IT Solutions Pvt Ltd.

Project Title : Building management System

: 5 Months 15 Days (January – June 2012)

Project Duration

Team Size : 5 members

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Project Objective : To visit clients sites and to prepare a report on their requireme nts and

manage things while installing our products and while giving customer

service support.

Working Areas : CCTV cameras, Fire alarm system, Home automation and Access

Control

Status of the project : Project was successfully completed

Internship 2

Organization : Visakhapatnam Steel Plant.

Project Title : SCADA and Wireless Communication System

Project Duration : 52 DAYS (June-July`10)

Team Size : 4 members

Project Objective : To observe SCADA & Wireless Communication system in

Visakhapatnam Steel plant & to prepare a report on its working

Status of the project : Project was successfully completed

Internship 3

Organization : JUST CHANGE (Non-Government Organization)

Project Title : The CARNIVAL Program

Project Duration : 53 DAYS (June-July`09)

Project Objective : To bring out the hidden talents in children, and to get sponsors for their

studies

Contribution : Team leader

VLSI & Software Exposure:

Operating Systems : Windows, UNIX.

Front-End Synthesis Tools : Cadence RTL Compiler.

Back-End Tool : Cadence Virtuoso, Cadence SOC Encounter, QRC, ETS

Scripting Language : TCL,SHELL.

Achievements / Extra-Curricular Activities:

Played for Visakhapatnam district U/14 Cricket Team

Participated in the 51st A.P state level Inter District U/17 swimming tournament.

Participated in the XIX Sub-junior inter district Tenni-koit championship2004

Won prizes in dancing at Techno-cultural & Talent Fest(Conducted at ICFAI UNIVERSITY

TRIPURA) and other collages

Elected as school SPL(School People Leader) through elections

Cultural member of Student Activity Council and initiated many ideologies

Participated in state level science fair

Organized ‘ICARIA 10’ a Techno-Cultural fest held from 18th to 21st

November, 2010

Organized ‘intra-university sports 2011 at ICFAI University Tripura

Declaration:

I hereby declare that all statements made above are true and complete with the best of my knowledge.

Date:

Place: Peddi Karthik Chandra

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