| Resume alert | Resumes 41 - 50 of 77 |
Digital Design,verilog,system verilog,Embedded c,Hardware design
Bengaluru, KA, India
... • Good knowledge in Static Timing Analysis (STA). • Good knowledge in architecture of Spartan6 (LX75 & LX45),Spartan3 and CPLD devices. • Good knowledge in Orcad Capture CIS tool. • Good knowledge in ARM based microcontrollers. • Fair enough ... - 2014 Dec 26
... • Good knowledge in Static Timing Analysis (STA). • Good knowledge in architecture of Spartan6 (LX75 & LX45),Spartan3 and CPLD devices. • Good knowledge in Orcad Capture CIS tool. • Good knowledge in ARM based microcontrollers. • Fair enough ... - 2014 Dec 26
Project High School
Bengaluru, KA, India
... • Familiar in resolving various timing (STA) issues in a chip. • Proficient in HSPICE simulator tool. Tools and Language detail Hardware Description Language : Verilog and VHDL (Beginner) EDA Tools : HSPICE Software Skills : C, Perl (Beginner) ... - 2014 Nov 23
... • Familiar in resolving various timing (STA) issues in a chip. • Proficient in HSPICE simulator tool. Tools and Language detail Hardware Description Language : Verilog and VHDL (Beginner) EDA Tools : HSPICE Software Skills : C, Perl (Beginner) ... - 2014 Nov 23
Design Engineer
Bengaluru, KA, India
... Performed D etour Nets Analysis in fix-cell DB and a ssisted the P& R team with critical movemen ts o f IPs in fix-cell sta ge Analysis of rou ting channels for congestion o Scrip ted fo r Channel Estimation in TCL to id entify and h ighlight ... - 2014 Oct 24
... Performed D etour Nets Analysis in fix-cell DB and a ssisted the P& R team with critical movemen ts o f IPs in fix-cell sta ge Analysis of rou ting channels for congestion o Scrip ted fo r Channel Estimation in TCL to id entify and h ighlight ... - 2014 Oct 24
Power Pvt Ltd
Bengaluru, KA, India
... Area of Interest Physical Design: Floor Planning, Placement, CTS, PnR, STA, Timing Closure Physical Verification: IR Drop Analysis, DRC. Skills Cadence RTL compiler, Cadence SOC Encounter, Synopsis ICC, STA VLSI Projects Profile Project # 1 : RTL to ... - 2014 Oct 06
... Area of Interest Physical Design: Floor Planning, Placement, CTS, PnR, STA, Timing Closure Physical Verification: IR Drop Analysis, DRC. Skills Cadence RTL compiler, Cadence SOC Encounter, Synopsis ICC, STA VLSI Projects Profile Project # 1 : RTL to ... - 2014 Oct 06
Design Engineer
Bengaluru, KA, India
... TOOLS & LANGUAGE SKILLS Subjects Digital Circuits, STA, Physical Design, ASIC, Verification. Programming Languages Verilog HDL, VHDL, System Verilog, C/C++, MATLAB. Front-end EDA Tools QuestaSim, ModelSim, Quartus II, Cadence NC Launch. Back-end EDA ... - 2014 Oct 04
... TOOLS & LANGUAGE SKILLS Subjects Digital Circuits, STA, Physical Design, ASIC, Verification. Programming Languages Verilog HDL, VHDL, System Verilog, C/C++, MATLAB. Front-end EDA Tools QuestaSim, ModelSim, Quartus II, Cadence NC Launch. Back-end EDA ... - 2014 Oct 04
Design Engineer
Bengaluru, KA, India
... test benches& Test benches in System Verilog Very good knowledge on Verification methodologies(UVM) Experience in using industry standard EDA tools for the Front-end Design and Verification Knowledgeable in STA concepts and timing calculations . ... - 2014 Oct 03
... test benches& Test benches in System Verilog Very good knowledge on Verification methodologies(UVM) Experience in using industry standard EDA tools for the Front-end Design and Verification Knowledgeable in STA concepts and timing calculations . ... - 2014 Oct 03
Engineer Project
Bengaluru, KA, India
... Synthesis Tool : Design Compiler (Synopsys)(Beginner), VCS(Synopsys) STA : Prime Time (Synopsys) (Beginner). Schematic /Layout Editor :Virtuoso (Cadence)(Beginner), Microwind,DSCH Load Balancing Tool : LSF (Load Sharing Facility) Qualification tool ... - 2014 Sep 29
... Synthesis Tool : Design Compiler (Synopsys)(Beginner), VCS(Synopsys) STA : Prime Time (Synopsys) (Beginner). Schematic /Layout Editor :Virtuoso (Cadence)(Beginner), Microwind,DSCH Load Balancing Tool : LSF (Load Sharing Facility) Qualification tool ... - 2014 Sep 29
Verification Engineer who needs to have diversified opportunities
Bengaluru, KA, India
... Cadence Encounter, Cadence virtuoso, Synopsys VCS Platforms : UNIX and Windows Protocols : AMBA, AHB, AXI Interests : DFT, SoC, STA, CTS, RTOS, Testability, Verification methodology AREAS OF STRENGTH * Good communication skills, deterministic, self ... - 2014 Sep 28
... Cadence Encounter, Cadence virtuoso, Synopsys VCS Platforms : UNIX and Windows Protocols : AMBA, AHB, AXI Interests : DFT, SoC, STA, CTS, RTOS, Testability, Verification methodology AREAS OF STRENGTH * Good communication skills, deterministic, self ... - 2014 Sep 28
Academic experience in physical design
Bengaluru, KA, India
... Excellent knowledge on VLSI, CMOS, Static Timing Analysis (STA) and Finite State Machine (FSM). . Understanding of Digital Electronics and academic experience in the field of Digital Systems Design. EDUCATION . M-TECH IN VLSI SYSTEMS WITH 8.50 CGPA ... - 2014 Sep 20
... Excellent knowledge on VLSI, CMOS, Static Timing Analysis (STA) and Finite State Machine (FSM). . Understanding of Digital Electronics and academic experience in the field of Digital Systems Design. EDUCATION . M-TECH IN VLSI SYSTEMS WITH 8.50 CGPA ... - 2014 Sep 20
Project High School
Bengaluru, KA, India
... Skills Summary Syatem Verilog UVM/SVT/OVM Verilog HDL Logic Design Perl RTL Design/Verification Finite State Machine NCVERILOG AXI/AHB Protocal Ethernet-10G Protocol ARC6.0 Processor GDDR5 Protocol GPIO/UART/WDT Block UVM Component CDC/STA ... - 2014 Sep 18
... Skills Summary Syatem Verilog UVM/SVT/OVM Verilog HDL Logic Design Perl RTL Design/Verification Finite State Machine NCVERILOG AXI/AHB Protocal Ethernet-10G Protocol ARC6.0 Processor GDDR5 Protocol GPIO/UART/WDT Block UVM Component CDC/STA ... - 2014 Sep 18