CURRICULUM VITAE

SreenivaS E

E-Mail Id: abqv00@r.postjobfree.com

Mobile No: +91-988*******

objective:

Seeking a responsible position in the field of VLSI Physical design where I

can utilize and enhance my technical skills and professional experience

towards the organization's success

PROFESSIONAL SUMMARY:

Total Years of Experience: 5+ Years

1. Intel India Pvt. Ltd: MAR' 2008 till date as Physical design engineer

> 5 Years of experience in physical design

- Working on the 4th generation graphics project, contributed to two

successful tape-outs. During the course I worked on technologies of

45nm, 22nm and 14nm.

- My expertise lies in handling physical design blocks for Synthesis,

placement and routing, CTS, FEV, STA, ECO implementations, power

analysis and Physical verification using the industry standard tools

like: DC-compiler (DC-T), IC-Compiler, Prime-time and Conformal-LEC

and other Intel internal tools

> Worked as an internship employee at Conexant systems for 6 months

EDUCATIONAL QUALIFICATIONS:

> MTech in VLSI Design from Sathyabama University, Chennai, May-2007

> MSc in Electronics technology from P B Siddhartha college of Arts &

Science, Vijayawada, AP, 2005

> Bachelors of science in Electronics technology from Loyola Academy,

Hyderabad, AP, 2003

Skill Set:

Back-end Tools : Synopsys IC Compiler, Star-RC and Carmel

Timing Engine : DC, ICC and Prime Time-SI

Front - end Tools : Design Compiler (DC-T), Conformal-LEC

Layout Tools : Genesys, IC-Compiler

Scripting Languages : Perl and TCL

OS Exposure : Solaris and Windows

Work Experience:

1. In progress on partitions/blocks for a graphics chip of 14nm

. Syn and ICC pre-cts routing iterations with the RTL models of every

milestone and adopt floorplan changes

. CSVs for PIN placement, Macro placement refinements, Unit and RP

placement refinements, also experimenting with multiple FP options

. RTL feedback based on the section level post-syn routed timing on the

Intra and Inter partition timing paths

. SYN and CTS RTL2Gate UNIT level FV for every FV RTL models

. DCU-DP timing budgeting refinements for timing and Gate Count

improvements at DCU and partition levels and addressing Unit placement

split issues at partition level, resolving placement and route

congestions and experiments for higher utilization targets

. Routing on Pre CTS db and section PT roll-up for addressing inter/intra

timing outliers and QoR for proceeding to clock-tree synthesis

2. Partition Level convergence on Gthspar1 in a graphics chip of 22nm

This partition contained around 1.2M gates, with the block dimensions of

1100umX600um. As part of the partition ownership, here I had involved in

performing the following:

. Block designed at 1.36 Ghz in a graphic chip

. Unit level placement by understanding and analyzing the lower unit/fub

level data connectivity, follow-up with RTL unit owners for better

understanding

. Partition level pins and Macro/EBB placement based on Unit placement

within and outside partitions, regular discussions with respective

stakeholders for inter-par/sec level pin placement

. Challenges in handling PD placement and timing with the significant RTL

changes and resolving issues with high cell density and route congestions

with Timing driven place & route

. RTL feedback to UO on the critical timing paths with more combo levels or

high complexity cells of logic, requesting for the side model RTL

releases

. Feed-thru and Relay buffer placement and routing for the inter-

par/section paths during initial placement

. Post-Route flows for timing and power convergence

. Performed timing and power analysis and their optimizations at all levels

3. Partition Level convergence on Gthsmpar4

This block contained around 1.4M gates, with a dimension is of

1000umX550um, and had 8 hard macros/EBBs.

. Unit level placement by understanding and analyzing the lower unit/fub

level data connectivity, follow-up with RTL unit owners for better

understanding

. Partition level pins and Macro/EBB placement based on Unit placement

within and outside partitions, regular follow-up with respective

stakeholders for inter-par/sec level pin placement

. Multiple techniques for the macro/EBB placements and partition pin

refinements to improve the routing quality and generating DEFs with

Incremental floorplan for various flavors of EBB placements

. Multiple PD experiments in adjusting the relative placement blocks and

EBB/Macro placements, targeting higher cell utilizations and DRCs/Shorts

convergence

. Contributed in floorplanning for the all the partitions in my section,

delivered collaterals to respective partition owners

. Scan stitching and reordering and Clock Tree Synthesis was performed and

optimized using Clock tree Mesh

. Timing and SI convergence at Par/Section/FC levels for different corners

was performed using ICC and PT-SI

4. ECO implementations on Gthspar1 and Gthspar4

This involved numerous ECO implementations for the graphics project

partitions, contributed in the ECO convergence which includes:

. ECO feasibility and the STCL preparation, FV checks between the DC Vs

ICC generated netlist. Syn_eco and Check_eco before the ICC eco

implementation

. Handled complex ECOs where involved 500-1500 new gates, regular follow-

up with RTL owners and organized extremely well in placement and

clocking, buffering and routeability

. Region based placement and routing using ICC to retain the previous

layout edits in non-ECO regions

. RTL2Gate, Gate2gate FV and signoff checks performed on the post-ECO

database

. Provided ECO STCL scripts to layout verification team to address minor

timing and quality violations.

5. Unit level Functional equivalence verification using Conformal LEC on

post Syn and post CTS netlists Vs RTL

. Unit level FV for all units at section level, debug and analyze to

resolve the aborts/failures and apply all techniques in resolving non-eq

points

. RTL2Gate FV execution on post-syn and post-cts netlist and Gate2Gate FV

for every model release

. Several challenges in handling the Abort units, multiple experiments

with different hierarchical flavors, renaming rules, mappings etc

. Enhanced the Vault script for generating the CTS-FV collaterals

6. Reliability verification and IR-Drop execution, Analysis and Fix

. Contributed in RV execution for several blocks using NETRV, Power-RV and

Carmel extraction tools

. NetRV and TavorPwr performs DC/RMS currents calculations on signal and

power nets, reports the IR drop, EM, SH and SF violations

. Knowledge on IR-drop, EM/SH checks using Redhawk

7. Physical verification on physical design partitions

. Involved in implementing the layout ECOs and cleaned the design for all

the physical verification flows

. Involved in various layout edits during ECO implementations, fixes like

DRC, LVS mis-match, Antenna, DFM, signal route improvements, shielding,

signal shorts/opens fix and many other edits for PV or for timing/SI

. Ownership of Physical design blocks for the Physical Verification

convergence

ACHIEVEMENTS

* Appreciated with Spontaneous recognition awards (SRA) for the complex

partition ECO implementation along with all checks, for debugging and

follow-up with stake holders related to flow/tool related issues

* Appreciated with Department recognition award (DRA) and couple of SRAs

for the ECO feasibility, route quality and FV Checks on a complex

partition

* Appreciated with multiple Goodie level awards for the partition ECO

convergence for place and route and quality/FV checks convergence

Personal Strengths and Weaknesses

* I am go-getter in life. Whatever I wish to achieve I go after that with a

single-minded devotion. I aspire to succeed in a competitive industry

environment as a team player. Bringing success to different tasks or

assignments gives me immense pleasure. I look for challenges in my

assignments - all problems are opportunities.

* My main strengths are my determination and will power to succeed.

Hypocrisy in people is what puts me off

Hobbies

Table tennis, Volley ball, Hand ball, Cricket, Carroms and Listening to

Music

Personal Profile:

DOB and Age : 30/08/1983 and 28 years

Current Location : Murgeshpalya, Bangalore -17

E-Mail ID : abqv00@r.postjobfree.com

Phone Number : +91-988*******

Contact this candidate