CURRICULUM VITAE

BHARATESH M SAGARE Mobile:+**-

741*******

Emailid:ab90jr@r.postjobfree.com

Objective:

Intend to build a career with leading corporate of hi-tech

environment with committed & dedicated people, which will help me to

explore myself fully and realize my potential. Willing to work as a key

player in challenging & creative environment.

Educational Qualification:

Qualification Institute Year Of Passing Percentage

Visvesvaraya

B.E (ECE) Technological 2010 71.38%

University

PU Board

Class XII Karnataka 2006 60.21%

KSSEB Bangalore

Class X 2004 78.88%

Skills:

Perl, Shell scripting, TCL, Python,Verilog,VHDL.

SPICE Coding HSPICE, SPECTRE, PSPICE.

Schematic circuit and layout design

DRC,LVS,RC Extractions

Standard cell characterization, SPICE Simulations

Strong Knowledge of CMOS Device Physics and CMOS basics.

CAD Tools Used HSPICE, SPECTRE,calibre,Hercules,virtuoso layout and

schematic editor, Mentor graphics Pyxis for layout and schematic editor.

I undergone training in :

Scripting Languages - Perl, Advanced Perl, Python, TCL.

HDL's and Simulation Concept - Verilog, VHDL, System Verilog .

Static Timing Analysis (STA).

SLF.

DRC and LVS checking.

Device Physics.

CMOS Logic Design.

Cell Library Design and characterization.

Testing and Verification.

Worked on 16-bit Full adder Design.

Tools Used Under Training:

Modelsim

VCS

Concorde

Design Compiler

Pspice

Ngspice

Magic Tool for layout

Xcircuit

Cadence Virtuoso schematic and layout.

Calibre For DRC and LVS checks.

Synopsys HSPICE

Spectre Circuit Simulator

Projects .1 : Currently Am Working in lp60 project using ALTOS Tool

Currently am working on lp60 project. Its low power library

characterization for different corners.

Worked in Standard cell circuit design for basic gates Inverter, NAND,

NOR, latch and D- flip flops using SPECTRE and HSPICE simulator tools with

meeting the delay and power parameters specified in the spec.

Complete layout and schematic circuit design for all the standard cells

using cadence virtuoso layout and schematic editor.

Worked in SRAM memory characterization Bitcell functionality

checking,read and write margin calculation and SNM for different PTV's.

Projects .2 : Worked in lp50 project using ALTOS Tool

Worked on standard cell characterization on ALTOS tool for 45nm technology

cells.

Laff to netlist extraction.

Creating setup for char run - cell template, cell func, slew load, cell

group file creation.

Used external SPICE simulator tool SPECTRE which is supported by ALTOS for

.lib generations.

Synopsys liberty format .lib generation,it contains all input pins cap,

cell leakage for different condition, internal power, transition delays,

cell delay, constraint delays, ccs data, noise etc.

Hold pad lib generation for only sequential cells.

Synopsys Library Compiler check, to check the syntax error checks for

generated .libs.

Other views generations EM, GOI, CDB, LEF, Dynamicir (Redhawk ).

IQC run, Integrated Quality check for the generated .libs,other views pin

consistency checks, attribute checks in .libs and other views.

MIC, Merged Integrity creation. Which creates the merged .libs PTV wise

and other views merging.

Final library CML creation and release the data.

Projects.3: Worked in lp503P3 project using ALTOS Tool

Worked on this project to generate synopsys liberty format .lib

generation for low leakage cells on 60nm.

Worked on this project to generate .libs for all the High Vt cells .

Complete char setup for ALTOS.

Netlist extraction from laff.

Synopsys .lib generation using SPICE simulator tool SPECTRE supported by

ALTOS.

Hold pad lib generation for only sequential cells.

Library compiler (Synopsys LC check) for liberty format syntax checks.

Other views generation EM, GOI, CDB, LEF, Dynamicir (Redhawk models).

IQC run, quality check.

Release2Design sync, which is run, once the quality check is done, we

release data to a common database, where other users or Designers can

easily accessible to the data any time.

MIC build, Merged Integrity create and final data release.

CML creation and final data release.

Projects.4 : Worked in gs70 project using Turbo char Tool

Worked on this project for library char of HVT, OHVT cells on 60nm, 70nm

and 120nm technology.

The library I worked on 120nm and 70nm technology is called a smart sight

char for low leakage PTV's only for HVT, OHVT, SVT, XLVT cells.

Worked on TURBO CHAR tool for cell characterization for generating Cin,

Cpd, Timing, Constraints.

Hold pad data generation for sequential cells.

Final Synopsys liberty format .lib generation by merging all the data .libs

generated separately.

Other views generations EM, GOI, CDB, Dynamicir (Redhawk Models).

Current Working Company : I am Working with Interra Systems, Bangalore for

TI Projects. I joined Interra Systems in 18th April 2011.

Professional Summary:

Worked on ALTOS characterization tool for standard cells on 45nm, 60nm

technologies.

Worked on TURBO char tool for standard cell characterization on 60nm, 120nm

technologies.

I have worked on CMOS circuit design and worked on synopsys HSPICE tool

writing HSPICE stimulus and running simulation, measuring transition delays

variation and other parameters for all standard cell gates.

Worked on cadence Virtuoso and mentor graphics Pyxis tool for schematic and

layout circuit design and Analog layout design with centroid matching

technique.

Good in shell scripting and Perl scripting I have done small scripting

codes in characterization and undergone training in python, TCL scripting

languages.

Good in CMOS Device Physics and basics of CMOS.

I am interested to work in I/O Char and Memory Characterization and

Standard cell Circuit Designing.

Worked on 45nm, 60nm, 120nm and 110nm technologies.

I have familiar with PSPICE coding and running simulations for basic CMOS

circuits and measuring delay the parameters.

Areas of Interest : I have done some circuit designing,memory char and

Analog layout with centroid matching techniques. Interested to work in the

circuit design, memory characterization, Analog layout Design. Waiting for

opportunities to work in these field.

Tools Used :

HSPICE and SPECTRE SPICE simulator tools for cell library characterization

and standard cell design.

Cadence VIRTUOSO and Mentor Graphics Pyxis for layout and schematic editor

For standard cell layout,SRAM control Block design and schematic editor

for standard cell circuit design and simulation.

Calibre for DRC and LVS checks.

Operating Systems:

MS Windows XP

MS Windows 98

Linux

Extra Curricular Activities:

Perceived embedded course with A+ from Pendulabs Bangalore.

Participated in national level tech fest "ZESTECHNIA".

Actively involved in social services like medical, educational track and

student mentoring program.

College Project:

Project Name: Intelligent Anti-Terrorist Robot

Description: This project is based on Atmels - 8051 controller. Heart of

IATR is AT-89c51 controller, IATR is GSM operated, microcontroller can be

used to control all the movements of robot and the actions are to be taken

by watching the real time audio and video information send by camera in CC

TV and based on this gun is triggered by operator in the control room.

Personal Profile:

Name : Bharatesh M Sagare

Father's Name : Mahaveer

Date of Birth : 09/04/1988

Languages Known : English, Kannada, Hindi, and Telugu.

Address for communication: #443,2nd floor, 8th Cross,

29th main BTM

Layout 2nd Stage,

Kuvempu Nagar

Bangalore-560076

Permanent Address : At.p/-Naganur, Jain galli

Ta/- Gokak

Di/- Belgaum

P in-591224

I hereby declare that the above written particulars are correct to best

of my knowledge

And belief.

Bharatesh .M.S

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