SAITEJA KOTTE

+91-903*******

acbqzf@r.postjobfree.com,

CAREER OBJECTIVE

Seeking a position where I can utilize my skills and abilities in the Industry that offers professional

growth while being resourceful, innovative, and flexible that helps to work to my full potential for

the growth of the organization along with my personal and professional growth

EXPERIENCE SUMMARY

TECHINCAL INTERN (Solutions Group) (1year 10 months)

Synopsys (India) Pvt Ltd, Bangalore.

• Involved in Mapper Verification and Validation of RTL synthesis products (synplify pro &

premier) and prototyping tool (certify).

• Responsible for Achronix/Synopsys OEM (synplify pro) build validation.

• Responsible for Lattice/Synopsys OEM (synplify pro) build validation

• Experienced in RTL coding in Verilog, synthesis, implementation and Optimization

• Involved in developing of Performance measurement suite for the tools that results in

QOR (time and memory consumption) using TCL Scripting

• Involved in creation of regression testcases in verilog for Autocompilepoint with effect of

attributes and cross checking the Rtl vs Netlist using VCS

POST GRADUATE DIPLOMA STUDENT (Aug 2011 - Jan 2012) (6 months)

SANDEEPANI SCHOOL OF VLSI DESIGN, Bangalore.

• Undergone training in Advance Digital Designing, Synthesis, STA, FPGA Architecture, TCL

scripting, Verification modules.

• Experienced in system verilog for creation of verification environment using OOPS

Concepts.

EDUCATIONAL QUALIFICATION

• Post Graduate diploma in VLSI Design and Verification from SANDEEPANI SCHOOL

OF VLSI DESIGN, Bangalore (Aug 2011- Jan 2012).

• Bachelor of Engineering (2007-2011) in Electronics and Communication from J.N.T.U,

Anantapur (GKCE) with an aggregate of 73.11%.

• Higher Secondary Education (2007) from Narayana Junior College, Nellore Andhra

Pradesh with an aggregate of 90.6%.

• S.S.L.C (2005) from Little Flower High School, Nellore, Andhra Pradesh with an aggregate

of 88.7 %.

WORK SUMMARY

My responsibilities and work towards improvement of my skills.

• Major role involved in creating testcases and verification of Auto compile point project

which results in better runtime of the larger designs along with QOR results.

• Creating test-cases for verifying attributes and synthesis change for new devices in OEM

(Synplify pro/Achronix devices), analyzing and regression of testcases.

• Writing reusable task based automated test benches using verilog.

• Analyzing synthesis results (for various constraints and attribute change).

• Developing scripts for automation using TCL scripting.

• Familiar with Xilinx Virtex-7 architecture and flow.

• Projects done

a. AMBA-APB design.

b. SYNCHRONOUS FIFO (design and verification).

SKILLS & PROFICIENCIES

HDLs : Verilog, System Verilog.

Language : C, TCL.

Platforms : Windows / Linux.

Tools : Synopsys synthesis (synplify pro and premier) and prototyping

(certify) tools, Modelsim, Xilinx Vivado, Achronix P&R tools.

Protocols : AHB

PROJECTS

VALIDATION OF AUTOMATIC COMPILE POINT FEATURE IN SYNPLIFY PREMIER

Description: Automatic Compile point is the feature in tool which enhances the run time of big

designs. Ensuring the attributes flow working smooth with effect of automatic compile point option

in Xilinx and Altera technology.

PERFORMANCE MEASUREMENT (IN TERMS OF TIME AND MEMORY

CONSUMPTION) FOR SYNPLIFY PRO AND PREMIER

Description: The main purpose of this suite is to measure the response times and memory

consumptions of GUI and TCL actions in tool from one build to other build for customer designs. It

monitors the fastness of tool and less memory consumption from one build to other build on user

performing actions.

HIGH RELAIBILTY DESIGN FEATURE IN SYNPLIFY PREMIER

Description: This feature ensures the reliability of design by monitoring the errors in different ways

such as DWR, DTMR, ECC and FSM. Created the testcases for error monitoring mechanisms and

converted them into regression format testcases

PHYSICAL PLUS FLOW FEATURE FOR SYNPLIFY PREMIER AND PREMIER_DP

Description: This feature uses the Edif inputs generated from logic synthesis with enhanced

optimization. It runs global placer and router providing placement and routing at the expense of

timing. This provides Quality of results (QOR) for the designs.

DECLARATION

I hereby declare that the above mentioned information is true to the best of my knowledge.

(SAITEJA KOTTE)

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