| Resume alert | Resumes 21 - 30 of 77 |
Test Project
Bengaluru, KA, 560001, India
... Tools Used: Cadence and Modelsim Tools: •Cadence NC-SIM,RTL Compiler (RC), HAL (Lint), STA, LEC •Xilinx Tools, Mentor Graphics. Education: B.E (E&C) from IETE --- CGPA 7.8 PG Diploma in VLSI Design --- Grade – A Diploma in IEE in Institute of ... - 2016 Oct 05
... Tools Used: Cadence and Modelsim Tools: •Cadence NC-SIM,RTL Compiler (RC), HAL (Lint), STA, LEC •Xilinx Tools, Mentor Graphics. Education: B.E (E&C) from IETE --- CGPA 7.8 PG Diploma in VLSI Design --- Grade – A Diploma in IEE in Institute of ... - 2016 Oct 05
Design Project
Bengaluru, KA, 560001, India
... Good understanding in fundamentals of Logic design, CMOS design and STA. Good knowledge on AMBA APB and AHB protocol. ACADEMIC QUALIFICATIONS: Qualification University/Board Year of passing Percentage Institution M.Tech (VLSI Design) V.I.T ... - 2016 Sep 20
... Good understanding in fundamentals of Logic design, CMOS design and STA. Good knowledge on AMBA APB and AHB protocol. ACADEMIC QUALIFICATIONS: Qualification University/Board Year of passing Percentage Institution M.Tech (VLSI Design) V.I.T ... - 2016 Sep 20
Project Design
Bengaluru, KA, 560001, India
... Hands on experience with Synthesis (RTL Complier),STA,DFT,,Place and Route . Knowledge of 45nm technology. Projects Handled: Project 1 : DTMF Core Physical Design implementation of DTMF Core in Cadence SOC Encounter DTMF Core is Dual Tone Multi ... - 2016 Jun 02
... Hands on experience with Synthesis (RTL Complier),STA,DFT,,Place and Route . Knowledge of 45nm technology. Projects Handled: Project 1 : DTMF Core Physical Design implementation of DTMF Core in Cadence SOC Encounter DTMF Core is Dual Tone Multi ... - 2016 Jun 02
Design Safety
Bengaluru, KA, 560001, India
... Knowledge of Memory design concepts (STA, Setup & Hold time). Good Knowledge of Digital Logic Design: Combinational Logic Circuits, Sequential Logic Circuits, Memories (SRAM) Knowledge of Embedded system design Operating Systems: Windows, Linux. ... - 2016 May 16
... Knowledge of Memory design concepts (STA, Setup & Hold time). Good Knowledge of Digital Logic Design: Combinational Logic Circuits, Sequential Logic Circuits, Memories (SRAM) Knowledge of Embedded system design Operating Systems: Windows, Linux. ... - 2016 May 16
Electronics Engineer
Bengaluru, KA, 560001, India
... Backend Proficiency : Physical Design, CTS, STA, DRC,LVS,ERC Operating Systems : Windows,Linux. Tools Used : Simulation & Synthesis Tools – PSPICE,orcad,Xilinx ISE 8.2i, Model Sim 10.1b, Precision Synthesis RTL 2012b.10. : Backend Tools -- Mentor ... - 2016 Apr 17
... Backend Proficiency : Physical Design, CTS, STA, DRC,LVS,ERC Operating Systems : Windows,Linux. Tools Used : Simulation & Synthesis Tools – PSPICE,orcad,Xilinx ISE 8.2i, Model Sim 10.1b, Precision Synthesis RTL 2012b.10. : Backend Tools -- Mentor ... - 2016 Apr 17
resume
Bengaluru, KA, 560001, India
... Basic Knowledge: Digital design concepts, CMOS fundamentals, ASIC Design flow, Physical Design & layout design Concepts, STA, Network analysis, Analog design Fundamentals, AHB & I2C protocols. EDA Tools Experience: Place & Route: IC Compiler ... - 2016 Feb 26
... Basic Knowledge: Digital design concepts, CMOS fundamentals, ASIC Design flow, Physical Design & layout design Concepts, STA, Network analysis, Analog design Fundamentals, AHB & I2C protocols. EDA Tools Experience: Place & Route: IC Compiler ... - 2016 Feb 26
Design High School
Bengaluru, KA, 560001, India
... Familiar with ASIC Design flow, STA and FPGA implementation. MATLAB Software Languages : Basics of c, Data structures, object oriented program(oops). Experience : During my training period from july 22 2015 to Jan 22nd, 2016 in Maven silicon ... - 2016 Feb 05
... Familiar with ASIC Design flow, STA and FPGA implementation. MATLAB Software Languages : Basics of c, Data structures, object oriented program(oops). Experience : During my training period from july 22 2015 to Jan 22nd, 2016 in Maven silicon ... - 2016 Feb 05
Project Engineer
Bengaluru, KA, India
... Checking the timing analysis (STA) report: setup and hold time check. Behavioral Simulation. Validating the design on the hardware. Project 2 : ATDL(Air Transport Data Link Layer) Transponder Project Development Tools : Xilinx ISE 12.2 Simulation ... - 2015 Dec 28
... Checking the timing analysis (STA) report: setup and hold time check. Behavioral Simulation. Validating the design on the hardware. Project 2 : ATDL(Air Transport Data Link Layer) Transponder Project Development Tools : Xilinx ISE 12.2 Simulation ... - 2015 Dec 28
Design Software
Bengaluru, KA, India
... Board Of Secondary Education 96.4 2009 Experience: Synopsys Inc., Bangalore June 22,2015 – Present Experience skills: Underwent training in the following industry standard EDA Synopsys tools PrimeTime Version 2014.06 Complete knowledge of STA flow. ... - 2015 Dec 13
... Board Of Secondary Education 96.4 2009 Experience: Synopsys Inc., Bangalore June 22,2015 – Present Experience skills: Underwent training in the following industry standard EDA Synopsys tools PrimeTime Version 2014.06 Complete knowledge of STA flow. ... - 2015 Dec 13
ASIC / FPGA design and verification trainee
Bengaluru, KA, India
... Skills VLSI Domain ASIC / FPGA front-end Design and Verification Technical knowledge RTL coding, Synthesis, FSM designs, Code Coverage, Functional coverage, CMOS, STA. HDL Verilog HVL System Verilog TB Methodology OVM (Open Verification Methodology) ... - 2015 Oct 22
... Skills VLSI Domain ASIC / FPGA front-end Design and Verification Technical knowledge RTL coding, Synthesis, FSM designs, Code Coverage, Functional coverage, CMOS, STA. HDL Verilog HVL System Verilog TB Methodology OVM (Open Verification Methodology) ... - 2015 Oct 22