V S BALASUBRAMANIAN

Mob: 91-888*******, E-mail: aby90p@r.postjobfree.com

Career Summary

Determined and result-oriented ASIC Design Engineer offering an

experience of 3+ years in Leading ASIC Design & IP Solutions Company.

With a experiential record I aspire to build a career with leading

corporate encompassing committed & dedicated people, which would help me

to harness my entire potential, skill sets, qualifications and creativity

for the growth and success of the organization.

Key Competencies and Skills

Core Competencies

. Digital design, memories, RTL, STA, validation of the timing reports,

SI analysis,

Physical design, Synthesis, Equivalence checks, Physical verification.

. DFT scan stitching and scan insertion.

. Hands on experience tools: Icc compiler, DC-Turbo and DC synthesis,

LEC, Formal Verification, Star Extraction, Calibre, Primetime, Magma

Talus, Syntest turbo.

Technical Skills

. Detailed Conversance with the Synopsys Physical Design flow.

. Detailed Conversance with the Magma Physical Design Flow

. EDA Tools: Detail knowledge of IC Compiler, Synopsys Integrated Floor-

planning, Place & Route Solution, Primetime, Static Timing Analysis

tool from Synopsys and STAR-RCXT, Magma-Talus, Formality, LEC,

Calibre, FE, CLP

. Experience of working on 65, 45nm, 32nm technology nodes.

. Programming and Scripting Languages: C, Perl, Tcl.

Ingenious problem finder, with capacities to lucratively point out errors

in early stages to avoid time/cost expenditures. Innovative and

exceptionally creative to foster ideas that impel the organization towards

a result-oriented direction. Impeccable management and leadership skills

with abilities to work independently as well as a team driven by new

challenges and adapting to any cultural and business environments.

Professional experience

Total Experience 3+ years

. As a Design Engineer, I run RTL2GDS, pin assignment for multi-million

gate SoCs.

. Have been through multiple design tapeouts on 65, 40nm & 28nm nodes.

. Perform floor planning, placement, CTS, routing, timing closure,

correlation, signal integrity analysis and physical verification.

. Have a Deep understanding of hierarchical/timing driven layout

methodologies for multi mode multi corner implementation on 65,40nm

technology nodes.

. Carry out Lower power implementation and simultaneous Multi mode multi

corner timing closure.

1. March, 2012-till date

Working as ASIC-Physical Design Engineer at Blackpepper Technologies

Project Name: Thorin

Team size: 5

Technology details: 28nm

. Implemented Multi display sub system of total 1100k instances and 105

memory count using FE Encounter for floorplanning and synopsis ICC

compiler for implementation.

. Performed congestion and timing driven placement.

. Worked on different CTS techniques to meet the previous insertion delays

and balance the skew.

. Routing and post-routing optimization for timing optimization using icc.

. Correlated the signoff Primetime results with the timing results in icc

. Performed Static timing analysis with Primetime/SI

. Hands on experience with the clp .

Project Name: G.hn

Team size: 3

Technology details: 65nm

. Implemented 1 block (400MHz) of total 500k instances using synopsis ICC

compiler from netlist to GDSII.

. Performed congestion and timing driven placement.

. Worked on different CTS techniques to meet the previous insertion delays

of taped out database

. Routing and post-routing optimization for timing optimization using icc.

. Correlated the signoff Primetime results with the timing results in icc

. Performed Static timing analysis with Primetime/SI

. Assisted on the top level DRC correlation issues across magma(previous

taped out database),icc and caliber

. Assisted on the top level max net length fixing of the data and clock

nets

2. Sep, 2010-Feb, 2012

Working as ASIC Design Engineer at Uniquify Inc

Project Name: Lahaina

Technology details: 65nm

. Implemented 3 blocks (500MHz) of total 2.1 million instances using Talus

from netlist to

GDSII.

. Performed Floor plan/Power plan by debugging congestion issues in the

design through

different floor plans, macro placements.

. Performed congestion and timing driven placement.

. Routing and post-routing optimization for timing optimization using

Talus.

. Correlated the signoff Primetime results with the timing results in

Talus Vortex

. Performed Static timing analysis with Primetime/SI

Project Name: Velocity3

Technology details: 40nm

. Implemented 5 blocks (600MHz) of total 3.5 million instances using Talus

from netlist to

GDSII.

. Performed Floor plan/Power plan by debugging congestion issues in the

design through different floor plans, macro placements.

. Performed block level Power and IR drop analysis

. Performed congestion and timing driven placement.

. Routing and post-routing optimization for timing optimization using

Talus.

. Correlated the signoff Primetime results with the timing results in

Talus Vortex

. Performed Static timing analysis with Primetime/SI.

Project Name: Xingtera

Technology details: 32nm

. Implemented 3 blocks (630MHz) of total 2 million instances using Talus

from netlist to GDSII.

. Performed Floor plan/Power plan by debugging congestion issues in the

design through

. different floor plans, macro placements with the design engineer

. Performed congestion and timing driven placement.

. Routing and post-routing optimization for timing optimization using

Talus.

. Performed parasitic extraction with Star RC

. Correlated the signoff Primetime results with the timing results in

Talus Vortex

. Performed Static timing analysis with Primetime/SI

3. Jan, 2010-Aug,2010

Intern at Intel technologies pvt ltd. India

Academic Qualifications

. MSP-MVD/M Tech in Microelectronics and VLSI Design, IIIT Pune.

. B.Tech - ECE (Electronics and Communication Engineering), STIET, JNTU,

Hyderabad.

Other interest and activities

. Organized corporate functions like Annual Day and Family Day.

. Organize the charity fund to orphans and disabled children's with the

help of friends and colleagues.

. Bike riding and exploit new places locally.

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