| Resume alert | Resumes 81 - 90 of 680 |
Project Design
Bengaluru, KA, India
... Programming Languages: C, Verilog, MATLAB, Microcontroller 8051. Software and Tools: Xilinx, Cadence Virtuoso. Digital System Design Using Verilog VLSI Verification, CMOS VLSI Design Logic Design OBJECTIVE EDUCATION QUALIFICATIONS SKILL SET SUBJECT ... - 2016 Jun 10
... Programming Languages: C, Verilog, MATLAB, Microcontroller 8051. Software and Tools: Xilinx, Cadence Virtuoso. Digital System Design Using Verilog VLSI Verification, CMOS VLSI Design Logic Design OBJECTIVE EDUCATION QUALIFICATIONS SKILL SET SUBJECT ... - 2016 Jun 10
Verilog, System Verilog, Uvm
Bengaluru, KA, 560001, India
... College 2009 90.9% X St Mary’s High school 2007 84.16% TECHNICAL SKILLS Knowledge in Building verification Environment in System Verilog Experience in writing RTL models in Verilog HDL and Test benches in System Verilog Experience in using industry ... - 2016 Jun 09
... College 2009 90.9% X St Mary’s High school 2007 84.16% TECHNICAL SKILLS Knowledge in Building verification Environment in System Verilog Experience in writing RTL models in Verilog HDL and Test benches in System Verilog Experience in using industry ... - 2016 Jun 09
VLSI Design/Verification Engineer
Bengaluru, KA, 560054, India
... Technical Skills CAD Tools: Cadence NCSim & NC-Verilog, Virtuoso, Encounter, Matlab & Simulink Modelling, Xilinx ISE, Vivado & SDK, Synopsys IC Compiler, NI LabVIEW, Mentor ModelSim Simulator. HDL/HVL Languages: VHDL & Verilog, System Verilog, UVM. ... - 2016 Jun 03
... Technical Skills CAD Tools: Cadence NCSim & NC-Verilog, Virtuoso, Encounter, Matlab & Simulink Modelling, Xilinx ISE, Vivado & SDK, Synopsys IC Compiler, NI LabVIEW, Mentor ModelSim Simulator. HDL/HVL Languages: VHDL & Verilog, System Verilog, UVM. ... - 2016 Jun 03
Project Design
Bengaluru, KA, 560001, India
... The design is taken from Sourcing the Verilog file to Generating a Gate Level Netlist. Synthesised RISC with the tcl script file with all the constraints from the input specification. The design is synthesized for Low Power . Generated Reports on ... - 2016 Jun 02
... The design is taken from Sourcing the Verilog file to Generating a Gate Level Netlist. Synthesised RISC with the tcl script file with all the constraints from the input specification. The design is synthesized for Low Power . Generated Reports on ... - 2016 Jun 02
Project Service Technician
Bengaluru, KA, 560001, India
... VLSI VERILOG & VHDL Programming. (Lab oriented) Embedded & Pic microcontroller Programming(Lab Oriented). Matlab & Quartus Verilog design(Lab Oriented). Microwind Cmos & Pmos Design & Digital Microwind Schematic. Micro controller & Xilinx Software ... - 2016 Jun 02
... VLSI VERILOG & VHDL Programming. (Lab oriented) Embedded & Pic microcontroller Programming(Lab Oriented). Matlab & Quartus Verilog design(Lab Oriented). Microwind Cmos & Pmos Design & Digital Microwind Schematic. Micro controller & Xilinx Software ... - 2016 Jun 02
Engineer Training
Bengaluru, KA, 560001, India
... Pursued VLSI Training From M S Ramaiah University Of Applied Science Good Knowledge on Digital Systems, FPGA, ASIC Basics Of C, HTML, Java Script -2- TECHNICAL SKILLS Programming Languages : JavaScript, HTML, Verilog HDL/RTL Coding, Basics Of C ... - 2016 May 31
... Pursued VLSI Training From M S Ramaiah University Of Applied Science Good Knowledge on Digital Systems, FPGA, ASIC Basics Of C, HTML, Java Script -2- TECHNICAL SKILLS Programming Languages : JavaScript, HTML, Verilog HDL/RTL Coding, Basics Of C ... - 2016 May 31
Embedded System Engineer. VLSI, Verilog, System Verilog, CMOS Design
Bengaluru, KA, 560001, India
... Technical Skills: Programming Languages : Verilog, System Verilog for verification, C, C++, Embedded C. EDA Tool : Xilinx, Cadence Virtuoso Design Tool, Questa Sim, Keil Micro Vision. Other Skills : Digital Design, CMOS Design, FPGA. Operating ... - 2016 May 30
... Technical Skills: Programming Languages : Verilog, System Verilog for verification, C, C++, Embedded C. EDA Tool : Xilinx, Cadence Virtuoso Design Tool, Questa Sim, Keil Micro Vision. Other Skills : Digital Design, CMOS Design, FPGA. Operating ... - 2016 May 30
Engineer Design
KA, India
... Technical Skills H/W Description Languages: VHDL, Verilog, System Verilog and System Verilog Assertions Other Languages : Matlab Simulator: Modelsim, from Mentor Graphics and Isim, Vivado Simulator from Xilinx Tools Used : Xilinx ISE, Vivado, ... - 2016 May 30
... Technical Skills H/W Description Languages: VHDL, Verilog, System Verilog and System Verilog Assertions Other Languages : Matlab Simulator: Modelsim, from Mentor Graphics and Isim, Vivado Simulator from Xilinx Tools Used : Xilinx ISE, Vivado, ... - 2016 May 30
High School Technical
Bengaluru, KA, 560001, India
... Tools : Mat lab, VHDL, Verilog. HOBBIES Listening songs. Reading books. Playing chess Strengths: Hardworking Positive thinking confidence PERSONAL PROFILE Name : T.SIVA SANKARA VARA PRASAD Father Name : T.SANKARAIAH Date of Birth : 21/05/1995 ... - 2016 May 29
... Tools : Mat lab, VHDL, Verilog. HOBBIES Listening songs. Reading books. Playing chess Strengths: Hardworking Positive thinking confidence PERSONAL PROFILE Name : T.SIVA SANKARA VARA PRASAD Father Name : T.SANKARAIAH Date of Birth : 21/05/1995 ... - 2016 May 29
Analog Design and Layout, VLSI design, Verilog
Bengaluru, KA, 560001, India
... ACADEMIC QUALIFICATIONS TECHNICAL SKILLS Design Skills Operating Systems EDA Tools Analog design, Layout, Verilog, ASIC, Basics in PERL, TCL DOS, Windows XP/7/8, Linux CADENCE® (Virtuoso, NC Launch, RC, Encounter) XILINX® ISE, Model Sim PROJECTS ... - 2016 May 27
... ACADEMIC QUALIFICATIONS TECHNICAL SKILLS Design Skills Operating Systems EDA Tools Analog design, Layout, Verilog, ASIC, Basics in PERL, TCL DOS, Windows XP/7/8, Linux CADENCE® (Virtuoso, NC Launch, RC, Encounter) XILINX® ISE, Model Sim PROJECTS ... - 2016 May 27