VLSI Design/Verification Engineer

Dhanya Hegde

***/*,*** *****, **** Main, Gokula *st Stage, 1st Phase, Bangalore { 560054.

************@*****.***, +919*********.

https://in.linkedin.com/in/dhanyahegde

Objective To seek a challenging career in the eld of Digital Circuit Design (Front-end/Back-end Design & Veri cation) by working with an Organization that allows me to use my skills, talent and technical abilities to add value and grow with the organization.

Technical Skills CAD Tools: Cadence NCSim & NC-Verilog, Virtuoso, Encounter, Matlab & Simulink Modelling, Xilinx ISE, Vivado & SDK, Synopsys IC Compiler, NI LabVIEW, Mentor ModelSim Simulator. HDL/HVL Languages: VHDL & Verilog, System Verilog, UVM. Programming Languages: C & C++.

Scripting Languages: Tcl, Shell, Perl.

Assembly Languages: 8086 & 8051.

Serial & Bus Protocols: AMBA AXI, AHB, APB, PCIe 3.0, I2C, SPI, RS232, USB, UART. Operating Systems: Linux Red Hat & Ubuntu, Windows Family. FPGA: Zynq 7000 Series (Zedboard & Microzed), Spartan 3E, Virtex 5. VLSI Front-end: ASIC/FPGA Design Flow, RTL Coding, FSM based designing, Functional Veri cation, Functional Coverage, Code Coverage, Assertions & Regressions, Test cases creation. VLSI Back-end: Synthesis, Physical Designing, LVS, DRC, Static timing analysis, Layout design. Experience Project Intern at Centre for Nano Science & Engineering, IISc August 2015-Present Designing a Network Processor on FPGA : Implemented HDL models for the functional designing & veri cation of a multimode System on Chip (SoC) for mobile devices. Integrated & designed the physical layer blocks within the base-band chip. Designing high performance cores & microengines that are replicated for use in next generation network processing, coordinating with rmware and package teams to set and meet aggressive area targets. Pin Planning & designing high speed I/O’s to meet the desired speci cation. Language: VHDL & Verilog

Project Trainee at Adventura Technologies(India) Pvt. Ltd., B’lore August 2013-July 2014 Veri cation of D-PHY: Cadence R MIPI R D-PHY IP integrates a MIPI high-speed transmitter and receiver that support data rates up to 1.5Gbps per lane, and a MIPI low-power transceiver that enables bidirectional data transfer. This IP was based on Version 1.1 of the MIPI D-PHY spec. The digital D-PHY was integrated and interfaced with controllers of MIPI CSI2 and DSI protocols. The architecture supported connection of multiple data lanes in parallel. Performed debugging, coverages & regressions to meet these speci cations.

Language: Verilog & System Verilog

Projects Veri cation of PCI Express Transmitter in Data Link layer August 2014-December 2014 PCI Express is a serial point to point link that operates at 2.5 Gbits/sec in each direction. PCIe Bus func- tional veri cation based on data exchanged between Tx & Rx using System Verilog and Cadence Simulator was carried out. The data link layer sends the layer Packets which indicate the amount of receiver bu er space available in units of credits. The transmitter had to ensure that the bu er space is not exceeded prior to commencing a transmission. Developed a test plan and setup the testbench and the Veri cation environ- ment, analyzed test results and performed coverage analysis. Wrote test cases to test the functionality of the modules & veri ed the same.

I2C Protocol Veri cation Environment Using UVM January 2015-May 2015 I2C (Inter-Integrated Circuit), is a multi-master, multi-slave, single-ended, serial computer bus. The bus is a multi-master bus which means any number of nodes can be present and is highly

exible & con gurable that it can be easily integrated into any SOC veri cation environment. Functional Veri cation of the bus using Cadence RTL Compiler was carried out.The coverage obtained was 100% for assertion based coverage and 90.15% functional coverage using UVM. The total coverage so obtained was 95.07%. DAQ System for environmental monitoring using GSA January 2013-June2013 The data from the sensors were collected by means of on-chip A/D converter and stored in a serial EEP- ROM until uploaded to a portable computer via RS232 serial port for subsequent analysis. Keeping the DAQ system in a low-power mode, which was only interrupted when measurements are to be taken or when a computer is connected to retrieve the stored data, minimized power consumption. An on-chip timer was provided as an interrupt to awaken the system from its low-power wait mode at 10-min intervals to sample and store the data. The Data Acquisition hardware were SUNROM IDAQ and the TARANG MODULE F20.The former was used for the wireline transmission of data and the latter was used for the wireless trans- mission of data using Labview.

Honors & Awards "URIn neon"-All India Student Technical Paper Presentation November 2014 Titlte:"Asymmetric Clock Driver for Improved Power Performances" in Low Powered Devices. Organizer: In neon Technologies India Pvt. Ltd

Position: Second Runner-up

Honor of Merit "INWES-National Conference for Paper/Poster Presentation" October 2012 Titlte:"Ozone Waste Water Treatment Solution"

Organiser: International Network of Women Engineers & Scientists(INWES), New-Delhi Education School Of Information Sciences, Manipal University 2014-2016 Master of Science in Technology(MSC.Tech, VLSI Design), 8.0 GPA (previous year) Currently working as Intern with Centre for Nano Science & Engineering, IISc Bangalore. S.C.T.I.T, Visvesvaraya Technological University 2009-2013 Bachelors in Electronics and Communications Engineering, 7.15 GPA. St. Claret College, Bangalore 2007-2009

Higher Secondary Education,Karnataka Board 60%

Kendriya Vidalaya IISc, Bangalore 1997-2007

Cleared All India Senior School Examination with 7.8 CGPA Declaration I here by declare that all the information presented here is true to best of my knowledge. Dhanya Hegde

Ph: 961*******

June 1, 2016

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