Project Design

SHABARISH E-mail: ************@*****.***

Phone: +91-991*******

To be a part of a professional organization where I can use my skills and abilities for the growth of the company.

Currently pursuing M.Tech (VLSI Design and Embedded Systems) in PES Institute of Technology, Bangalore (2014-16). Aggregate 75.5%(Upto 3rd SEM)

Working as an Intern at Certitude Technologies Pvt Ltd, Bangalore.

Cleared the Graduate Aptitude Test in Engineering (GATE 2014) with AIR 20877 and a GATE score of 406.

Obtained B.E.(Electronics and Communication) from Bapuji Institute of Engineering and Technology, Davangere. (Affiliated to VTU), in year 2013 With Aggregate of 81.32%.

Passed 12th (Karnataka State Board) From PSSR Junior College, DAVANGERE, Karnataka in year 2009 With 76.84%.

Passed 10th (Karnataka State Board) From SES ENGLISH MEDIUM SCHOOL, Siruguppa, Bellary, Karnataka in year 2007 with 84.32%.

Programming Languages: C, Verilog, MATLAB, Microcontroller 8051.

Software and Tools: Xilinx, Cadence Virtuoso.

Digital System Design Using Verilog

VLSI Verification, CMOS VLSI Design

Logic Design

OBJECTIVE

EDUCATION QUALIFICATIONS

SKILL SET

SUBJECT OF INTEREST

“FEEL Employable”- stage I learning and development intervention conducted from 30 March to 01 April 2012, at BIET from CHLRD.

Attendance Management Using Face Recognition Using MATLAB: Project describes a method for Student’s Attendance System which will integrate with the face recognition technology. Managing student attendance during lecture periods has become a difficult challenge. The ability to compute the attendance percentage becomes a major task as manual computation produces errors, and also wastes a lot of time. For the stated reason, an efficient attendance management system using biometrics is designed. Biometric time and attendance system is one of the most successful applications of biometric technology, serves as an alternate for traditional manual process.

MTECH PROJECT:

Reconfigurable Floating Point Pipelined Vedic Multiplier: Project describes a reconfigurable floating point multiplier implemented on FPGA with custom floating point format for different applications. This floating point multiplier can have 6 modes of operations depending on the accuracy or application requirement. With the use of optimal design with custom IPs (Intellectual Properties), a better implementation is done by truncating the inputs before multiplication. Karastuba algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier. For exponent addition carry look ahead adder is used. This further increases the efficiency of the multiplier. The multiplier is pipelined so that performance is improved.

Reading Novels(Non-fictional), Cricket, Music

I hereby declare that above mentioned information are true as per my knowledge. SHABARISH

ACADEMIC PROJECTS

TRAINING UNDERGONE

PERSONAL INTERESTS

DECLARATION

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