| Resume alert | Resumes 71 - 80 of 680 |
Verification Engineer
Bengaluru, KA, 560001, India
... Experience and knowledge in UNIX,Linux,Synopsis Tools,Verilog and C. Experience in ARM/AMBA Proessor system. Experience in ASIC Verification,Develop test plans. Experience in Functional Coverage and Code coverage. Good understanding of the ASIC and ... - 2016 Aug 11
... Experience and knowledge in UNIX,Linux,Synopsis Tools,Verilog and C. Experience in ARM/AMBA Proessor system. Experience in ASIC Verification,Develop test plans. Experience in Functional Coverage and Code coverage. Good understanding of the ASIC and ... - 2016 Aug 11
Design High School
Bengaluru, KA, 560001, India
... Hardware Languages : Verilog, MATLAB. EDA Tools : Cadence Virtuoso, Encounter, Synopsys HSPICE, Cosmos-scope, Xilinx ISE. RELATED COURSE WORK Basic VLSI Design, Advanced VLSI Design, Design of Analog and Mixed Mode VLSI Circuits, Digital System ... - 2016 Jul 27
... Hardware Languages : Verilog, MATLAB. EDA Tools : Cadence Virtuoso, Encounter, Synopsys HSPICE, Cosmos-scope, Xilinx ISE. RELATED COURSE WORK Basic VLSI Design, Advanced VLSI Design, Design of Analog and Mixed Mode VLSI Circuits, Digital System ... - 2016 Jul 27
Design Electrical
Bengaluru, KA, 560001, India
... STRENGTHS 1.Communication Skills 2.Leadership 3.Teaching 4.Programming languages : Verilog, VHDL, C++ 5.Tools Used: Xilinx, Tanner, Cadence(Virtuoso, Encounter), Microwind, Spice tools 6.Operating System : Microsoft Windows,Linux. 7.Computer ... - 2016 Jul 25
... STRENGTHS 1.Communication Skills 2.Leadership 3.Teaching 4.Programming languages : Verilog, VHDL, C++ 5.Tools Used: Xilinx, Tanner, Cadence(Virtuoso, Encounter), Microwind, Spice tools 6.Operating System : Microsoft Windows,Linux. 7.Computer ... - 2016 Jul 25
VLSI Engineer
Bengaluru, KA, 560001, India
... Experience in RTL Design verification and validation, test cases and testbench development Good Knowledge of VHDL and Verilog Good Knowledge of MATLAB /Simulink Knowledge of Assembly languages programming, System Verilog HDL and UVM Programming ... - 2016 Jul 21
... Experience in RTL Design verification and validation, test cases and testbench development Good Knowledge of VHDL and Verilog Good Knowledge of MATLAB /Simulink Knowledge of Assembly languages programming, System Verilog HDL and UVM Programming ... - 2016 Jul 21
Design Engineer
Bengaluru, KA, 560001, India
... Strong in Digital design, Micro-Architecture Design using VHDL, Verilog. Waveform analysis &debugging skills using Chip scope, Signal Tap. Worked on Ethernet, AMBA AHB/AXI, Ethernet, UART, and I2C. Good Exposure of RTL Design, Simulation, Debugging, ... - 2016 Jul 07
... Strong in Digital design, Micro-Architecture Design using VHDL, Verilog. Waveform analysis &debugging skills using Chip scope, Signal Tap. Worked on Ethernet, AMBA AHB/AXI, Ethernet, UART, and I2C. Good Exposure of RTL Design, Simulation, Debugging, ... - 2016 Jul 07
Design Engineer
Bengaluru, KA, 560001, India
... Experience Summary: 2+ year experience in RTL Design and Verification using VHDL / Verilog / System Verilog. Experience in writing test benches, automation scripts and regression Test Suite. Experience with Verification of protocols IPs like UART, ... - 2016 Jun 29
... Experience Summary: 2+ year experience in RTL Design and Verification using VHDL / Verilog / System Verilog. Experience in writing test benches, automation scripts and regression Test Suite. Experience with Verification of protocols IPs like UART, ... - 2016 Jun 29
verilog,system verilog, vlsi cad
Bengaluru, KA, 560001, India
... Modified carry select adder design, Hardware Engeering Aug – Dec 2014 Created a design to give lesser power, area and delay results of about 50% reduction and implementation using verilog. Worked on the cadence tool and mentor graphics tool(digital ... - 2016 Jun 20
... Modified carry select adder design, Hardware Engeering Aug – Dec 2014 Created a design to give lesser power, area and delay results of about 50% reduction and implementation using verilog. Worked on the cadence tool and mentor graphics tool(digital ... - 2016 Jun 20
Project Engineering
Bengaluru, KA, 560001, India
... Areas of Interest Electronics Digital Systems VLSI Verilog Co curricular Activities Presented the paper entitled “Analysis of Segmentation Techniques for Breast Cancer in Mammogram Images” in the 2nd National Conference at Saveetha Engineering ... - 2016 Jun 19
... Areas of Interest Electronics Digital Systems VLSI Verilog Co curricular Activities Presented the paper entitled “Analysis of Segmentation Techniques for Breast Cancer in Mammogram Images” in the 2nd National Conference at Saveetha Engineering ... - 2016 Jun 19
Project Design
Bengaluru, KA, 560001, India
... 90.40% Technical Skills Languages: C, VHDL, Verilog, Micro controller MATLAB SIMULINK Subjects of Interest Embedded Systems Logic Design Analog and Low power VLSI Computer Proficiency: Well versed in applications of Microsoft Excel, Outlook, ... - 2016 Jun 14
... 90.40% Technical Skills Languages: C, VHDL, Verilog, Micro controller MATLAB SIMULINK Subjects of Interest Embedded Systems Logic Design Analog and Low power VLSI Computer Proficiency: Well versed in applications of Microsoft Excel, Outlook, ... - 2016 Jun 14
VLSI, verilog, physical design
Bengaluru, KA, 560001, India
... Programming Languages: Verilog, C. CERTIFICATES / COURCES: Cource done on “Physical Design” in “Kanada Technologies” for the duration of 6 months from July to December 2015. Inplant Training in ITI LIMITED, Bangalore Plant Dooravaninagar, Bangalore. ... - 2016 Jun 13
... Programming Languages: Verilog, C. CERTIFICATES / COURCES: Cource done on “Physical Design” in “Kanada Technologies” for the duration of 6 months from July to December 2015. Inplant Training in ITI LIMITED, Bangalore Plant Dooravaninagar, Bangalore. ... - 2016 Jun 13