| Resume alert | Resumes 111 - 120 of 678 |
Engineer Design
Bengaluru, KA, 560001, India
... SKILLS Domain ASIC Front end Design and Verification Technical knowledge RTL coding, Synthesis, FSM designs, Code Coverage, Functional coverage HDL Verilog HVL System Verilog TB Methodology UVM(Universal Verification Methodology) Verification ... - 2016 Apr 04
... SKILLS Domain ASIC Front end Design and Verification Technical knowledge RTL coding, Synthesis, FSM designs, Code Coverage, Functional coverage HDL Verilog HVL System Verilog TB Methodology UVM(Universal Verification Methodology) Verification ... - 2016 Apr 04
Verilog, system verilog, uvm
Bengaluru, KA, 560001, India
... Experience in writing RTL models in Verilog. VLSI Domain Skills: HDL: Verilog HVL: SystemVerilog Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology: UVM Protocols: SPI, ETHERNET, ROUTER EDA ... - 2016 Apr 01
... Experience in writing RTL models in Verilog. VLSI Domain Skills: HDL: Verilog HVL: SystemVerilog Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology: UVM Protocols: SPI, ETHERNET, ROUTER EDA ... - 2016 Apr 01
Project Engineering
Bengaluru, KA, 560001, India
... Knowledge about Verilog,System Verilog,Perl. CO CURRICULAR Volunteer in college fest ‘SANSKRUTI’. Participated in How to sell yourself and Nail the interview workshop. Volunteer in National conference NEWS-2014. Participated in college Dramas and ... - 2016 Mar 30
... Knowledge about Verilog,System Verilog,Perl. CO CURRICULAR Volunteer in college fest ‘SANSKRUTI’. Participated in How to sell yourself and Nail the interview workshop. Volunteer in National conference NEWS-2014. Participated in college Dramas and ... - 2016 Mar 30
Design System
Bengaluru, KA, 560001, India
... Experience: Having 4 months Internship in Inspire IT Global Services Institute, Hyderabad Domain Skills: Tools : Xilinx, micro wind Programming Languages :C, Verilog, VHDL, System verilog Scripting Language :Shell, Perl, Unix Command on Logic Design ... - 2016 Mar 14
... Experience: Having 4 months Internship in Inspire IT Global Services Institute, Hyderabad Domain Skills: Tools : Xilinx, micro wind Programming Languages :C, Verilog, VHDL, System verilog Scripting Language :Shell, Perl, Unix Command on Logic Design ... - 2016 Mar 14
Assistant Design Engineer and working on iris recognition project
Bengaluru, KA, 560057, India
... ASIC Design Tool: Cadence Tool chain Simulation Tools: Modelsim, Isim, Simulink Familiar with Verilog, VHDL and TCL script languages Custom IC design flow from Schematic design to Post layout simulation Operating System: Windows XP/7/8, Linux Strong ... - 2016 Mar 12
... ASIC Design Tool: Cadence Tool chain Simulation Tools: Modelsim, Isim, Simulink Familiar with Verilog, VHDL and TCL script languages Custom IC design flow from Schematic design to Post layout simulation Operating System: Windows XP/7/8, Linux Strong ... - 2016 Mar 12
fresher
Bengaluru, KA, 560001, India
... State Board 2010 86.33% S.S.L.C GHGHS State Board 2009 93.60% Technical Skills: C language, Java Basics, Verilog, Arduino programming, Assembly level language Projects: Final year project- Embedded system for water quality detection and analysis. ... - 2016 Mar 11
... State Board 2010 86.33% S.S.L.C GHGHS State Board 2009 93.60% Technical Skills: C language, Java Basics, Verilog, Arduino programming, Assembly level language Projects: Final year project- Embedded system for water quality detection and analysis. ... - 2016 Mar 11
High School Design
Bengaluru, KA, 560001, India
... Technical Skills Tools/EDA Tools : Cadence, Assura, Xilinx HDLs : Verilog HDL, VHDL. Languages : Programming in C, Assembly Languages (8051 and 8086). Operating System : Windows 7, Windows XP, Linux. Good knowledge in designing schematic in Cadence. ... - 2016 Mar 09
... Technical Skills Tools/EDA Tools : Cadence, Assura, Xilinx HDLs : Verilog HDL, VHDL. Languages : Programming in C, Assembly Languages (8051 and 8086). Operating System : Windows 7, Windows XP, Linux. Good knowledge in designing schematic in Cadence. ... - 2016 Mar 09
Student
Bengaluru, KA, 560001, India
... SKILL SET: Software Tools: CADENCE,XILINX,MATLAB,SILVACO Programming Languages: C,VHDL,VERILOG Declaration: All the above mentioned information is true to my knowledge, no false information has been provided. Signature: Yathish.V - 2016 Mar 09
... SKILL SET: Software Tools: CADENCE,XILINX,MATLAB,SILVACO Programming Languages: C,VHDL,VERILOG Declaration: All the above mentioned information is true to my knowledge, no false information has been provided. Signature: Yathish.V - 2016 Mar 09
Project Engineer
Bengaluru, KA, 560001, India
... Brief Overview Expertise in writing RTL modules in Verilog HDL and Testbenches in System Verilog. Good Working knowledge of different Hardware Boards. Good understanding of ASIC and FPGA flow. Excellent understanding of Digital Design, CMOS, ... - 2016 Mar 08
... Brief Overview Expertise in writing RTL modules in Verilog HDL and Testbenches in System Verilog. Good Working knowledge of different Hardware Boards. Good understanding of ASIC and FPGA flow. Excellent understanding of Digital Design, CMOS, ... - 2016 Mar 08
Engineer Test Cases
Bengaluru, KA, 560001, India
... TECHNICAL SKILLS Operating Systems : Windows 8, UNIX Software Skills : C, C++ Hardware Verification Language : System Verilog, UVM, OVM Scripting Tools : Perl Scripting Protocol : AXI, APB Tools : Questa – Mentor Graphics VCS – Synopsys TRAININGS ... - 2016 Mar 02
... TECHNICAL SKILLS Operating Systems : Windows 8, UNIX Software Skills : C, C++ Hardware Verification Language : System Verilog, UVM, OVM Scripting Tools : Perl Scripting Protocol : AXI, APB Tools : Questa – Mentor Graphics VCS – Synopsys TRAININGS ... - 2016 Mar 02