Verilog, System Verilog, Uvm

Pudota Vineesha

**************@*****.***

Mobile No: +91-916*******

OBJECTIVE

Highly motivated, creative, versatile professional seeking challenging career in a highly esteemed organization that gives me a platform to use my expertise skills for mutual growth and benefit of organization and myself.

EDUCATIONAL QUALIFICATIONS

Qualification

Institution

Year of Passing

Performance

M.Tech(VLSI)

Jawaharlal Nehru Technological University, Hyderabad

2015

75.54%

BE (Eectronics)

Jawaharlal Nehru Technological University, Hyderabad

2013

79.08%

XII

Vignan junior College

2009

90.9%

X

St Mary’s High school

2007

84.16%

TECHNICAL SKILLS

Knowledge in Building verification Environment in System Verilog

Experience in writing RTL models in Verilog HDL and Test benches in System Verilog

Experience in using industry standard EDA tools for the front-end design and verification

Developed RTL codes for M.Tech academic VLSI projects

Strong fundamental understanding of RTL simulation and verification methodologies

Experience with RTL (Verilog) coding and synthesis

Experience with Xilinx, Modelsim and Questasim development tools

VLSI DOMAIN SKILLS

HDLs : Verilog HDL, VHDL

HVL : System Verilog HVL, UVM

EDA Tools : Xilinx ISE, Modelsim, Questasim.

Domain : IP/SoC Validation/Verification, ASIC/FPGA Design Flow

Knowledge : Verilog Coding, Synthesis, Simulation

INTERNSHIPS

Project Title: Network Router Switch - verification

Organisation: Smart Chip Design Bangalore

Duration: Jan 2016 – continuing

Project Description: The router accepts data packets on a single 8-bit Input port and routes the packets to one of four Output channels according to destination address.

Architected the class based verification environment using System Verilog HVL

Verified the RTL model using System Verilog

Generated Functional and code coverage for the RTL verification sign off

ACADEMIC PROJECTS:

B.TECH PROJECT:

Title : PH-SENSING TAG FOR WIRELESS FOOD QUALITY-MONITORING

Description: In this project a certain protocol will be followed to each and every food items.Items should have one tag, and the tag will have the information about the food item. In this we demonstrated and compared the pH values of soft drink, milk and orange.

M.TECH PROJECT:

Title : DESIGN OF A REVERSIBLE FLOATING POINT ADDER

Description: Reversible circuits offer the possibility for great reduction in power consumption. Modern computers consume a lot of energy, but devices based on reversible logic could reduce waste to zero.

EXTRA CURRICULAR ACTIVITIES

Participated in the seminar in OU titled “ IMAGE PROCESSING”

Participated in “WIE-CONGRESS -12” held by IEEE-WIE at GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING AND TECHNOLOGY

Won prize in District level competition of KHO-KHO held at school level

PERSONAL INFORMATION

Date of Birth: 14-06-1992

Gender : Female

Domicile: Andhra Pradesh

Marital Status: Married

Languages Known: English, Telugu

I hereby declare, that all the above given information are true to the best of my knowledge.

Pudota Vineesha

Place: Bangalore

Date: 09 June 2016

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