| Resume alert | Resumes 81 - 90 of 199 |
Design Electrical Engineering
Los Angeles, CA
... C, Verilog, PL/SQL, C#,VHDL, Python Applications and Tools: .Net, Modelsim, Cadence Virtuoso, Xilinx ISE, Lab Windows, Kiel, Prime Time, Design Compiler, Conformal, Synopsys, Cadence First Encounter Full Custom Design of pipelined processor. ... - 2017 Aug 17
... C, Verilog, PL/SQL, C#,VHDL, Python Applications and Tools: .Net, Modelsim, Cadence Virtuoso, Xilinx ISE, Lab Windows, Kiel, Prime Time, Design Compiler, Conformal, Synopsys, Cadence First Encounter Full Custom Design of pipelined processor. ... - 2017 Aug 17
Engineering Design
Fullerton, CA
... analyzer drive TECHNICAL SKILLS Programing Tools Lab OS Protocol: Development and Equipment’s: and Applications: IDE: languages: Platform: C, Cadence Windows, LTE, Oscilloscope, FPGA, C++SPI,, Arduino, VHDL, RS232, Virtuoso, Unix/Spectrum Verilog, ... - 2017 Aug 04
... analyzer drive TECHNICAL SKILLS Programing Tools Lab OS Protocol: Development and Equipment’s: and Applications: IDE: languages: Platform: C, Cadence Windows, LTE, Oscilloscope, FPGA, C++SPI,, Arduino, VHDL, RS232, Virtuoso, Unix/Spectrum Verilog, ... - 2017 Aug 04
Cisco Certified Network Associate
Los Angeles, CA
... Knowledge of Cisco Packet Tracer, LINUX, Verilog, Xilinx ISE, MATLAB, MAXWELL 14.0, ANSYS, OPNET, Computer technologies, applications & languages such as C, Eclipse, Code Blocks. Flair of utilizing modern principles, techniques and methods in ... - 2017 Jul 12
... Knowledge of Cisco Packet Tracer, LINUX, Verilog, Xilinx ISE, MATLAB, MAXWELL 14.0, ANSYS, OPNET, Computer technologies, applications & languages such as C, Eclipse, Code Blocks. Flair of utilizing modern principles, techniques and methods in ... - 2017 Jul 12
CCNA
Los Angeles, CA
... SKILLS: ● Programing Language: Socket Programming with Python, C++, C, Verilog, VHDL, Object Oriented Programming, CLI. ● Software Tools: GNS3, Putty, Microsoft Visio, Solar Winds Management, OPNET, MATLAB, WANDL, Xilinx XSE, LABVIEW, Keil, PSpice. ... - 2017 Jul 03
... SKILLS: ● Programing Language: Socket Programming with Python, C++, C, Verilog, VHDL, Object Oriented Programming, CLI. ● Software Tools: GNS3, Putty, Microsoft Visio, Solar Winds Management, OPNET, MATLAB, WANDL, Xilinx XSE, LABVIEW, Keil, PSpice. ... - 2017 Jul 03
Design Project
Placentia, CA, 92870
... Physical CMOS layout: Microwind VHDL/Verilog Simulator: ModelSim, GHDL, Xilinx Vivado. SPICE Simulator and Schematic Editor: LTSpice HDL’s: VHDL, Verilog HDL. NetBeans IDE, HyperTerminal. Software Programming Languages C, C++ Core/Advance JAVA ... - 2017 Jun 24
... Physical CMOS layout: Microwind VHDL/Verilog Simulator: ModelSim, GHDL, Xilinx Vivado. SPICE Simulator and Schematic Editor: LTSpice HDL’s: VHDL, Verilog HDL. NetBeans IDE, HyperTerminal. Software Programming Languages C, C++ Core/Advance JAVA ... - 2017 Jun 24
Engineer Electrical Engineering
Rancho Palos Verdes, CA
... Xilinx and Altera FPGAs, Lab Integration, SystemVerilog/C/Perl/assembly/Matlab, UART/1553/PCI/RS485/Ethernet, RTL (VHDL and Verilog), DFT_FastScan, Command and Data Handling system, Digital Signal Processing PROFESSIONAL EXPERIENCE Lockheed Martin, ... - 2017 Mar 29
... Xilinx and Altera FPGAs, Lab Integration, SystemVerilog/C/Perl/assembly/Matlab, UART/1553/PCI/RS485/Ethernet, RTL (VHDL and Verilog), DFT_FastScan, Command and Data Handling system, Digital Signal Processing PROFESSIONAL EXPERIENCE Lockheed Martin, ... - 2017 Mar 29
Engineer Design
Fullerton, CA
... Summary Of Experience FPGA and ASIC Design Aerospace/Defense Image Processing Printing Technology Board Level Design VHDL & Verilog EDA Tools Xilinx Vivado, ISE, CoreGen, and ChipScope Pro Tools Altera Quartus Actel/Microsemi Libero Software ... - 2017 Mar 28
... Summary Of Experience FPGA and ASIC Design Aerospace/Defense Image Processing Printing Technology Board Level Design VHDL & Verilog EDA Tools Xilinx Vivado, ISE, CoreGen, and ChipScope Pro Tools Altera Quartus Actel/Microsemi Libero Software ... - 2017 Mar 28
FPGA / ASIC Design Engineer
Fullerton, CA
Stephen Cole **** ********** ***, *********, ** *2835 Email: aczhiq@r.postjobfree.com Relevant Qualifications: ASIC / FPGA Design Engineer with over 15 years’ experience of design, implementation, simulation and co-verification of Verilog and VHDL ... - 2017 Mar 25
Stephen Cole **** ********** ***, *********, ** *2835 Email: aczhiq@r.postjobfree.com Relevant Qualifications: ASIC / FPGA Design Engineer with over 15 years’ experience of design, implementation, simulation and co-verification of Verilog and VHDL ... - 2017 Mar 25
Design State University
Fullerton, CA
... Embedded Systems field where my technical and analytical skills will be utilized to the maximum advantage of the organization and have 5 years of academic experience in these field with various languages knowledge like Verilog, System C and Python. ... - 2017 Mar 16
... Embedded Systems field where my technical and analytical skills will be utilized to the maximum advantage of the organization and have 5 years of academic experience in these field with various languages knowledge like Verilog, System C and Python. ... - 2017 Mar 16
Matlab, PSpice, hardware, circuit design, gate level logic design
Long Beach, CA
... & Networks, Microprocessor & Interfacing, Microcontroller & Interfacing Technical Skills Programming Languages: VHDL, Verilog, System Verilog, C, C++, Python, Matlab, LabVIEW Simulators: Microwind, DSCH, Xilinx ISE, Xilinx Vivado, Keil uVision, ... - 2017 Feb 11
... & Networks, Microprocessor & Interfacing, Microcontroller & Interfacing Technical Skills Programming Languages: VHDL, Verilog, System Verilog, C, C++, Python, Matlab, LabVIEW Simulators: Microwind, DSCH, Xilinx ISE, Xilinx Vivado, Keil uVision, ... - 2017 Feb 11