Krupa Bhavsar

https://www.linkedin.com/in/krupabhavsar

acyrvz@r.postjobfree.com 562-***-**** Long Beach, CA Education

California State University, Long Beach January 2017 Masters of Science, Electrical Engineering GPA: 3.6 Related Coursework: CMOS Electronics, Mixed Signal IC Design, Microelectronics, Analog Signal Processing, RF and Microwave Electronics, Network Theory, Advanced System Engineering Gujarat Technological University January 2014

Bachelor of Engineering, Electronics and Communication Engineering GPA: 3.7 Related Coursework: VLSI Technology & Design, Antenna & Wave Propagation, Digital Signal Processing, Digital Communication, Digital Logic Design, Circuits & Networks, Microprocessor & Interfacing, Microcontroller & Interfacing Technical Skills

Programming Languages: VHDL, Verilog, System Verilog, C, C++, Python, Matlab, LabVIEW Simulators: Microwind, DSCH, Xilinx ISE, Xilinx Vivado, Keil uVision, Modelsim, PSpice, NI Multisim, Agilent Advanced Design Systems (ADS), Altium Designer

Assembly Languages: 8085, 8086, 8051

Hardware: FPGA-Spartan 3E, Spartan 6, Nexys 4, Artix-7, Altera Quartus II Test and Measurement Equipments: Spectrum Analyzer, Network Analyzer, Function Generator, Oscilloscope, Logic Analyzer, Signal Generator, Multimeters

Verification Methodologies: OVM and UVM

Communication Protocols: I2C, SPI, PCIe, TCP/IP, Ethernet, USB, Wifi Publication

K. S. Bhavsar, H. G. Yeh, and P. Ayala "An aided information to characterize ECG signals as normal or abnormal," in IEEE International Symposium on Circuits and Systems, Baltimore, Maryland, 2017 (under review).

Certifications

OVM and UVM Test-benches, SOC Verification using System Verilog, VLSI Academy – Signal Integrity, Physical Design Flow, Clock Tree Synthesis; VHDL Design for use in FPGA and ASIC Digital Systems (License No: UC-EAHNP2HU); Python, Scilab, and Linux

Research

Application of Wavelet on Quasi-Periodic Physiologic Signals August 2015 – January 2017

Developed an efficient tool to determine normality or abnormality of the Electrocardiogram (ECG) signals based on estimation of its intervals using signal processing of the wavelets

Designed ECG signal synthetically in Matlab to realize its morphology

Discrete wavelet transform of the orthogonal Db4 wavelet was used to remove the artifacts present in the ECG signals for accurate detection its peaks

Eliminated the random white Gaussian noise by using the soft threshold denoising technique of wavelets for accurate detection of P-R, R-R, and P-P intervals present in the ECG signals

Detected peaks of the R-waves and P-waves with the hard threshold technique of wavelets

Measured the variation in the intervals to determine the normality or abnormality of the ECG signals

Obtained optimum results by testing the developed algorithm on eight different signals

Tolerance of 2 units was observed in the estimation of the mentioned intervals Relevant Experience

Teaching Associate California State University Long Beach CA January 2016 – December 2016

Conducted laboratory sessions of C++ language and Matlab software for undergraduate students

Developed numerous visible and hidden test cases in Matlab Cody Coursework to develop problem solving skills of the students

Taught students to code in a correct format, motivate them to develop their own logic, troubleshoot and implement several projects

Solved queries of the students and grade them according to their performance and progress

Assisted professor with course prospectus

Trainee Engineer Mega Switchgears India July 2013 – March 2014

Automated the system by programming the Allen Bradley Programmable Logic Controller (PLC) and tested it on Altera Quartus II FPGA

Monitored and rectified interlocking and tripping faults of the system

Layout of the system was designed on the Human Machine Interface (HMI) along with color codes

When a fault occurred in the system, a message along with the color change in the layout was displayed on HMI

Stored the system’s performance every two hours by connecting the USB drive with the HMI display

Operated the system from a remote location by connecting a LAN cable to the HMI display VLSI Lab Assistant Gujarat Technological University India August 2012 – December 2012

Assisted Professor in executing Verilog files on Spartan 3E and Spartan 6 FPGA in several class projects Relevant Projects

SDRAM Controller using Verilog January 2015 - May 2015

Designed a SDRAM controller in Verilog, implemented the algorithm on Altera Quartus II FPGA, and verified the design in Modelsim

RF Microwave Circuits using Agilent Advanced Design Systems (ADS) January 2015 - May 2015

Measured the input impedance of the transmission line and microstrip line as a function of frequency using the Line Calc function

Designed a matching network at 10 GHz by using the lumped elements and microstrip line for matching a 50 Ω feed line to the load

Designed a microwave amplifier at the center frequency of 2 GHz using the maximum gain approach

Designed an open-circuited λ/2 resonator and short-circuited λ/4 resonator with a coupling gap of 5um, measured its 3-dB bandwidth, tuned its gap in the range of 1-100 um to observe the changes in the resonant frequency, and performed momentum simulations

Learning Objective: Smith chart, transmission & microstrip lines, waveguides, microwave network analysis, impedance matching, tuning, coupling gap, momentum simulations, resonant frequency, 3-dB bandwidth Sampling Time Uncertainty in Switched Capacitor & Current Circuits January 2015 - May 2015

Verified the analytical operation of the voltage and current mode sampling circuits in Matlab

Compared the effect of signal dependent jitter on the switched capacitor, switched current and fully differential mode switched current sample and hold circuits

Performed the simulations to observe signal to noise ratio versus clock fall time for both the circuits

Learning Objective: Matlab, working of switched capacitor and current circuits, simulations Transistor Level Simulations of CMOS Circuits January 2015 - May 2015

Simulated various CMOS circuits namely, current mirrors, current sources, current sinks, cascode amplifiers, current amplifiers, output amplifiers, and differential amplifiers using Level 3 SPICE (45nm Technology)

Observed and compared Voltage Transfer Characteristics (VTC) and transient analysis of the circuits

Observed DC operating point and scaled the output up to 3V

Learning Objective: PSpice simulation, CMOS logic, VLSI Design, VTC, transient analysis, gate-level logic design

Charge Redistribution in Serial Digital to Analog Converter August 2014 - December 2014

Constructed a control unit for Digital to Analog Converter (DAC), and generated separate input lines for all the switches during each phase of the clock cycle in Microwind

Performed the simulations and observed the analog voltage at the output (45nm Technology)

Analyzed the effects of Integral Nonlinearity (INL), Differential Nonlinearity (DNL), and capacitor ratio mismatch error on the performance of the DAC

Learning Objective: layout, Verilog code, designing parallel to serial converter, DAC, INL, DNL, RTL, DSCH Flash Analog to Digital Converter August 2014 - December 2014

Designed a flash Analog to Digital Converter (ADC) using priority encoder novel algorithm in Microwind (45nm Technology)

Calculated the total chip area and power consumption of the ADC

Learning Objective: DRC rule check in Microwind, using DSCH, creating layout, working of ADC, RTL, DSCH Serial In Parallel Out Shift Register August 2014 - December 2014

Designed a 4-bit serial in parallel out (SIPO) shift register using D flip-flop in Microwind (45nm Technology)

Learning Objective: Microwind, DSCH, D flip-flop, serial in parallel out shift register, 45nm technology node

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