Stephen Cole

**** ********** ***, *********, ** *2835

Email: aczhiq@r.postjobfree.com

Relevant Qualifications: ASIC / FPGA Design Engineer with over 15 years’ experience of design, implementation, simulation and co-verification of Verilog and VHDL RTL designs for use in highly configurable custom embedded System On Chip (SOC) applications. Personal characteristics include being self-directed, innovative and energetic, good at recognizing, analyzing and solving problems, good oral communication skills, and is a dynamic player and excels whether working as part of a team, or on an individual basis.

EXPERIENCE

FRESENIUS MEDICAL CARE

80 Empire Dr., Lake Forest, CA, 92630 (Present)

Global Research and Development Division (GRD)

Senior Electrical Engineer / Senior FPGA Engineer

My primary responsibilities include working with managers and engineers across different disciplines to help define requirements and changes for various electronic subsystems in a new medical device. As such I was responsible for taking the requirements and carrying the project through design, development, test and transfer to manufacturing. The focus of my role is in the design, implementation, and testing of embedded systems, utilizing Xilinx FPGA’s with a specific focus on commercial medical applications where safety and reliability issues are of primary concern.

DRS TECHNOLOGIES

10600 Valley View Ave, Cypress, CA (2/08-4/13)

DRS Technologies: Surveillance and Targeting Systems

(DRS is a wholly owned subsidiary of Italian defense conglomerate Finmeccanica)

Senior FPGA Engineer / Senior Logic Design Engineer

My primary responsibilities included the design, implementation and testing of various embedded systems, utilizing Xilinx and Altera FPGA's primarily focused on military applications requiring real time video capture and processing, and the underlying high speed communication architectures used for the relaying of data. During my tenure at DRS, I developed the following innovative solutions:

Managed a IR&D project to develop a 10Gbps bidirectional single fiber optical reference platform for future designs, complete with 10G Ethernet and XAUI IP, and a fiber optic rotary joint (slip ring).

Developed a High Speed Serial Link (HSSL) interface - a platform independent packet communication system consisting of a 8b/10b encoder/decoder as well as a SerDes permitting board to board communication over LVDS in instances where standard serial interfaces were not feasible.

Developed a primitive graphics engine that interfaced to a Xilinx MPMC based multi-processor embedded system, which was used to overlay font data onto various live video streams.

Designed a Low Latency Ethernet (LLE) firmware module that could be used with a 10/100 or 10G MAC, permitting Ethernet functionality without requiring CPU intervention.

Authored / developed several internal engineering DO-254 process guidelines, training materials for other engineers, and a library of re-usable firmware code.

Lead a Trade Study on high speed serial communication protocols and interfaces

Developed several ongoing designs utilizing the Xilinx Virtex 7 and Zynq-7000 series of FPGA devices.

Worked diligently to install last minute major features in one of our products sent to the 2010 AUSA (Association of the U.S Army) trade show; which resulted in additional sales of the system and increased profits for the company.

As the EE Design group's EDA tools lead and Unix System Administrator, I was able to re-negotiate software licensing terms with our Xilinx vendor on 10 ISE/EDK tool licenses, saving the company approximately $24k.

INNOVATIVE INTEGRATION

2390 Ward Ave, Simi Valley, CA (2/05-2/08)

Senior Engineer (FPGA Design and Verification Engineer)

My primary responsibilities included the design, implementation and testing of logic for PCI based embedded digital signal processing and control systems used in a variety of development and OEM applications serving a large array of engineering disciplines.

Designed PCI and PCIE framework logic that was used on a variety of PCI platforms.

Responsible for most of the development on an elastic buffer, that utilized external DDR2 memory as a giant configurable buffer space.

Developed most of the logic for a DSP-based flight computer, contracted by Alliant Techsystems (ATK).

Aided in the development of custom and standard bus interfaces and other embedded design modules utilizing high speed memory and I/O interfaces used in other products.

Responsible for co-verification using C++ and Code Composer to verify various designs, utilizing internal hardware testing modules, and data generators for verification.

Developed various product release documentation.

LSI LOGIC CORPORATION

765 Sycamore Dr, Milpitas, CA (8/04-2/05)

Coreware / RapidChip Division (Contract Position)

ASIC Design and Verification Engineer

My primary responsibilities included the design, architecture, specification, and implementation of the System Verification Environment, integration and testing of various RTL block level modules, as well as debugging and verification of a multi-channel SerDes framer.

Worked on the design and verification of LSI’s RapidChip Xtreme Hydra HyperPhy Coreware slice, using LSI GFLX 130nm library.

Developed the verification environment to test the SFI-4.1, SONET/SDH, and other proprietary interfaces of the Hydra slice – with speeds ranging from 155Mbps to 3.1104Gbps on up to 20 channels over a 4 to 16 bit parallel to serial interface.

Enhanced and verified the AMBA (ARM) back-end user interface of the framer, and the system verification environment.

Responsible for testing the HyperPhy slice using the LSI RapidBuilder, and DFT FAST methodology, focusing on IP tests that will be used on customer ASICs and standard products.

Performed RTL / GATE and SVE regression testing.

Development of the RapidChip release documentation for the SerDes framer.

MAGNETO-INDUCTIVE SYSTEMS LIMITED

330 North D St., Suite 502, San Bernardino, CA (12/03-6/04)

Electronics Design Engineer

My primary responsibilities included research on the optimization, miniaturization, and on prototyping various facets of a unique military communication system.

Responsible for evaluating trade-offs in digital encoding schemes, methods to reduce power, and on the viability of parts.

Responsible for design analysis, prototyping various designs in accordance to design for test (DFT) and design for manufacture methodologies, verification and testing, as well as other associated tasks.

CADENCE DESIGN SYSTEMS

3030 Old Ranch Parkway, Suite 210/300, Seal Beach, CA (4/00-9/03)

Field Solutions Create Division (Formerly JTA Research Inc.)

ASIC Design Engineer / Digital Logic Design Engineer

My primary responsibilities included the design, architecture, documentation, implementation and verification of VHDL and Verilog RTL modules for use in various ASIC projects.

Designed, implemented and verified: a 16xN bit Error Detection And Correction (EDAC) module [single correction, double detection] (VHDL), a Wishbone to AMBA bus converter, and a Verilog four-channel DMA controller (AMBA AHB bus), along with an external bridge interface and additional FIFO control logic allowing the Verilog design to be integrated with up to 4 Ethernet MAC's (Verilog).

Debugged early versions of the LEON2 (32bit RISC SPARC V8, ARM AMBA compliant, OpenCore) processor, and other IP cores used in Cadence's R&D Eagle design platform) for the Eagle ASIC project (130nm TSMC, 5.29M gates, >100 MHz system clock (7 clock domains).

Synthesized, verified, tested, provided timing analysis, firmware support and implemented requested hardware (functional) upgrades to the previously designed AMBA bus four-channel DMA controller, for use in Cadence's R&D Condor ASIC project (130nm TSMC, 1.41M instances, >200 MHz system clock (5 clock domains), USB, VGA, DMA, IDE, DSP, CPU, Tripple-DES, 8 Ethernet MAC’s).

Simulated, linted IP blocks (using SpyGlass and Cadence HAL linting software), corrected problems that would effect synthesis, our design for test methodology, or the functionality of the blocks, and provided expert user feedback on all EDA tools used throughout the design process, and submitted suggestions for future EDA tool improvements.

Implemented various simulation, verification, and synthesis methodologies, as well as co-verification via firmware code in C and Assembly to test the various cores used in the Condor ASIC project, writing module specific stress cases in embedded software to verify the integrity and performance of various IP blocks.

Worked on a design contract with Raytheon on the F-22 Common Integrated Processor (CIP), developed as “the brain” of the Air Force's F-22 Raptor avionics.

Worked on Northrop Grumman's "CEUASIC" Project, under contract with JTA Research Inc.

EDUCATION

CSU Long Beach: B.S. Computer Engineering with Emphasis in IC Design, 5/2000.

Designed a digital audio recorder, as an elective under the guise of a senior design Project Utilizing Xilinx Prototyping Board with 3.3V, 20,000-gate FPGA and 128 KByte RAM, utilizing by Xilinx's Foundation and Alliance Series tools.

Educated in digital circuit design, timing analysis, compiler construction, use of In-circuit emulators (ICE) and Logic Analyzers.

Programmed, tested connectivity and worked on numerous projects with 8051 microcontrollers and CPLD’s in an academic setting utilizing proto/bread-boarding kit.

TECHNICAL EXPERTISE

EDA Tools

Xlinx : ISE (14.6), EDK, PlanAhead, Vivado

Altera : Quartus II, some exposure to Quartus SOPC Builder (Cyclone 3, Stratix 4)

Cadence : NC simulator(NC-SIM), HAL linter, Conformal(Verplex) verification tools, Ambit, BuildGates, PKS, some exposure to Cadence Layout and Routing tools (SOC Encounter).

Other Vendors: Synopsys Design Compiler, Synopsys VCS, Mentor Modelsim, Aldec Riviera, Atrenta SpyGlass linting software, some exposure to LogicVision, OrCad, Matlab, Code Compser, and VxWorks

Languages and Methodologies

VHDL, Verilog, TCL, C, System-C, Sugar assertion language, Unix & Linux scripting,

[Csh, Bash, Sh], Assembly language (8051, 8086, SPARC V8), ADA, Fortran, Firmware development using & C/C++, and Perl.

Familiar with DO-254, Design For Test (DFT) and Boundary Scan Testing Methodologies; Packet based communication systems, ARM’s AMBA (AHB/APB) bus interfaces, the Wishbone bus protocol; in addition to ASIC, FPGA and CPLD design, synthesis and verification methodologies.

Overview:

Mr. Stephen Cole, Senior Logic Design Engineer, has 17 years of experience developing electronic circuits for embedded systems for both the defense and commercial sectors. His areas of expertise span programmable logic design of ASIC and FPGA devices for use in highly configurable custom embedded system-on-chip (SOC) applications. His programmable logic experience includes the design, implementation and testing of various embedded systems, utilizing Xilinx and Altera FPGA's primarily focused on military applications requiring real-time video capture and processing. Specific examples include the design and development of a stack-less 10G Ethernet communication reference platform using a single bidirectional optical fiber, a high-speed serial platform-independent packet communication system, and the design, implementation and testing of logic for PCI and PCIe based embedded control systems. Mr. Cole has also developed hardware methods for error detection and correction as well as several internal engineering DO-254 process guidelines and training materials for other engineers. He has led numerous trade studies covering logic interfaces, protocols digital encoding schemes, and methods for power reduction. Over the years, Mr. Cole has developed electronic circuits for such organizations as DRS Technologies: Surveillance and Targeting Systems (a wholly owned subsidiary of Italian defense conglomerate Finmeccanica), Innovative Integration, LSI Logic, Magneto-Inductive Systems, and Cadence Design Systems (formerly JTA Research). Mr. Cole holds a B.S. in computer engineering from the California State University at Long Beach, California. Mr. Cole is a U.S. citizen.

OVERVIEW OF APPLICANT:

ASIC / VLSI / SOC / IC / FPGA / Digital Logic Design Engineer

US Citizen

Desired Status: Permanent / Direct Hire

Career Level: Mid Career (15+ Years of Experience)

Date of Availability: Open

Locations: Southern California :

North Orange County (i.e. Irvine, Newport Beach, Costa Mesa, Lake Forest, etc.)

East Los Angeles County (i.e. Long Beach, Azusa, etc.)

(25 Mile radius from Zip Code 92869)

Relocation Preferences: Unable to relocate out of the locations above.

References and Samples of previous work available upon request.

Skill Keywords: VHDL; Verilog; FPGA design, synthesis and verification; Xlinx (14.7): ISE, EDK (XPS), PlanAhead, Vivado; Altera Quartus II, SOPC Builder; ASIC; Cadence NC, Conformal, Ambit, BuildGates, PKS, Encounter; Synopsys DC, VCS; Mentor Modelsim; Aldec Riviera; LogicVision; OrCad; Matlab; Code Compser; VxWorks; TCL; C; scripting [Csh, Bash, Sh]; DFT; DO-254; ARM; AMBA, ASIC, CPLD

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