Design State University

KASHYAP PATEL

Willing to relocate 714-***-****

https://www.linkedin.com/in/kashyap-patel-498a5968 aczb0d@r.postjobfree.com

PROFESSIONAL SUMMARY

Seeking an interesting and challenging entry-level position in the field of ASIC design, VLSI design or Embedded Systems field where my technical and analytical skills will be utilized to the maximum advantage of the organization and have 5 years of academic experience in these field with various languages knowledge like Verilog, System C and Python.

SUMMARY OF SKILL

Languages: Verilog, VHDL, C and C++, System C, System Verilog, 8051(assembly), Python.

Tools: MATLAB, HSpice, Cadence Virtuoso, LTSpice, Kiel Compiler, Electric CAD, Skada, Multisim, ModelSim.

Others: Image processing using MATLAB, Programmable logic controller, SoCs.

Platforms: Windows, Linux, Mac OS.

WORK EXPERIENCE

Project Intern AUTOMATION ENGINEERS, Gujarat, India 01/13 - 05/13

Pursued training in embedded system and ASIC design field which include a design of code for any logic circuit.

Training included working on shop floors, learning about various tests and application of Embedded System and VLSI.

Completed project on Automatic toll collection system. Also prepared design code using Kiel Compiler and used μvision IDE tool to create embedded system program. GSM system and RFID system is also one of the main parts of this project.

PROJECTS

Digital Clock and Stop watch using Verilog HDL. 01/12 - 12/12

Used Verilog HDL programming in ModelSim and designed Digital Clock as well as a stop watch.

Performed this Verilog HDL code on nexus board.

Used operating frequency at 1 GHz.

XOR gate and 1-bit Full Adder using GDI technique. 02/16 - 10/16

Designed XOR gate and 1-bit Full adder using GDI technique and compared with CMOS, CPL and Double-Gate logic.

Used HSpice simulation tool with 22nm technology and 32 nm technology to check power dissipation and delay.

Got 60% - 80% reduction in power consumption and 80% - 85% reduction in delay for both cases using GDI technique.

A 6-bit Dual Slope Analog-to-Digital converter in 0.18um CMOS. 02/15 - 05/15

Designed a Control logic and counter for 6-bit dual slope A to D convertor.

Simulated the logic design in cadence virtuoso tool as per specifications.

Developed a schematic and layout design with specific design rules & matched LVS report successfully for both designs.

ACADEMIC TERM PAPERS

SRAM design using CNTFET and FinFET. 08/16 - 11/16

Designed 6-T and 8-T SRAM using CNTFET and FinFET and used HSpice simulation tool for simulation.

Reduced power dissipation up to 0.49μW using CNTFET and 0.21μW using FinFET.

Worst-case delays are decreased 88% for CNTFET and 74% for FinFET compare to CMOS technology.

Expansion of Caches for the super scalar processor. 08/15 - 12/15

Designed expanded cache models, Epic superscalar model, reorder buffer model, expanded cache reorder buffer model.

Expanded caches with In-order and Out-order way and gained 37% improvement by In-order and 43% by Out-order.

EDUCATION

Master of Science in Computer Engineering 01/15 – 12/16

California State University, Fullerton GPA: -3.50/4.00

Bachelor of Engineering in Electronics and Communications GPA: -3.51/4.00

COURSE WORK

Microprogramming and Embedded Microprocessors

Embedded Systems

Advance Computer Architecture

Introduction to Logic Design in Nanotechnology

Digital Design using HDL

VLSI and Nano-Technology Devices

Microprocessor Architecture & programming

Advance Microprocessors & Microcontrollers

Low Power Digital IC Design

Advanced Nano electronics

Mixed-Signal IC Design

VLSI Testing and Design for Testability

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