| Resume alert | Resumes 51 - 60 of 199 |
Data Entry
Carson, CA
... in the following programs/languages: Microsoft Word Microsoft Excel SQL Server 2012 Tableau Axure Google Map Engine VHDL Verilog C C++ Python MIPS Matlab Simulink Education BS in Computer Engineering California State University Bakersfield, ... - 2018 Dec 27
... in the following programs/languages: Microsoft Word Microsoft Excel SQL Server 2012 Tableau Axure Google Map Engine VHDL Verilog C C++ Python MIPS Matlab Simulink Education BS in Computer Engineering California State University Bakersfield, ... - 2018 Dec 27
Software Engineer
Los Angeles, CA
... PROGRAMMING SKILLS PROGRAMMING LANGUAGES C/C++ Python MySQL Schell Script Java Ocaml MongoDB PHP Lisp JavaScript HTML/CSS Verilog RELATIVE PLATFORMS & ENVIRONMENTS Docker Nodejs Angular Git Linux OSX PROJECTS Random Number Generator Summer 2018 ... - 2018 Dec 17
... PROGRAMMING SKILLS PROGRAMMING LANGUAGES C/C++ Python MySQL Schell Script Java Ocaml MongoDB PHP Lisp JavaScript HTML/CSS Verilog RELATIVE PLATFORMS & ENVIRONMENTS Docker Nodejs Angular Git Linux OSX PROJECTS Random Number Generator Summer 2018 ... - 2018 Dec 17
Engineer Computer Engineering
Compton, CA
... Systems TCPIP Python 3.6 Course Projects Designed and implemented a traffic light controller using a FPGA board in Verilog Designed and implemented a digital clock in Verilog Hands on experience with standard electronics lab equipment, FPGAs, ... - 2018 Nov 15
... Systems TCPIP Python 3.6 Course Projects Designed and implemented a traffic light controller using a FPGA board in Verilog Designed and implemented a digital clock in Verilog Hands on experience with standard electronics lab equipment, FPGAs, ... - 2018 Nov 15
Electrical Engineer Microsoft Office
Garden Grove, CA
... Master Cam v7, Multisim7 (PC Board design, layout, assembly, schematic documentation), Nios II IDE, Altera Quartus II version 6.0 (Field-programmable gate array, Verilog Hardware Description Languages), Pbasic Stamp, MikoC (Microchip programmers). ... - 2018 Nov 07
... Master Cam v7, Multisim7 (PC Board design, layout, assembly, schematic documentation), Nios II IDE, Altera Quartus II version 6.0 (Field-programmable gate array, Verilog Hardware Description Languages), Pbasic Stamp, MikoC (Microchip programmers). ... - 2018 Nov 07
Electrical Engineering Design
Los Angeles, CA
... SKILLS Verilog, System Verilog, UVM, C, C++, Python Platforms Cadence Virtuoso, Cadence Innovus, Modelsim, Questasim, Ubuntu, Xilinx Vivado, Visual Studio, Matlabs. PROJECTS Software: Conducted Sort Algorithms, Link list, Graphs(BFS, DFS), Regular ... - 2018 Oct 30
... SKILLS Verilog, System Verilog, UVM, C, C++, Python Platforms Cadence Virtuoso, Cadence Innovus, Modelsim, Questasim, Ubuntu, Xilinx Vivado, Visual Studio, Matlabs. PROJECTS Software: Conducted Sort Algorithms, Link list, Graphs(BFS, DFS), Regular ... - 2018 Oct 30
Student
Los Angeles, CA
... an efficient sorting method • Prepared advertisements for lab equipment on LabX and Ebay platforms SKILLS • Technical: MATLAB, Verilog, R, Python, SolidWorks, Excel, PowerPoint • Communication: Technical Writing, Public Speaking, Debate LEADERSHIP ... - 2018 Sep 27
... an efficient sorting method • Prepared advertisements for lab equipment on LabX and Ebay platforms SKILLS • Technical: MATLAB, Verilog, R, Python, SolidWorks, Excel, PowerPoint • Communication: Technical Writing, Public Speaking, Debate LEADERSHIP ... - 2018 Sep 27
Assistant Engineering
Los Angeles, CA
... Spring 2017 - Design the MIPS in Verilog to be programmed onto an Altera DE0. Awards and Seminars • Presidential Volunteer Service Award (2) August 2014 – May 2015 - Preparation and management in North Campus STEM and environmental club’s events. • ... - 2018 Aug 08
... Spring 2017 - Design the MIPS in Verilog to be programmed onto an Altera DE0. Awards and Seminars • Presidential Volunteer Service Award (2) August 2014 – May 2015 - Preparation and management in North Campus STEM and environmental club’s events. • ... - 2018 Aug 08
Design Electrical Engineering
Los Angeles, CA
... HSPICE Design Synthesis using Synopsys Design Compiler Signal processing and simulation on MATLAB Front-end RTL design using Verilog HDL/VHDL Static Timing Analysis with Synopsys Primetime Place and Route using Cadence Encounter (EDI) Functional ... - 2018 Jul 17
... HSPICE Design Synthesis using Synopsys Design Compiler Signal processing and simulation on MATLAB Front-end RTL design using Verilog HDL/VHDL Static Timing Analysis with Synopsys Primetime Place and Route using Cadence Encounter (EDI) Functional ... - 2018 Jul 17
Electrical Engineer Manufacturing
Fullerton, CA
... Aced in programming competitions - C/ C++, Assembly and System Verilog. - 2018 Jul 17
... Aced in programming competitions - C/ C++, Assembly and System Verilog. - 2018 Jul 17
Design Electrical Engineer
Manhattan Beach, CA, 90266
... Software Language Proficiency: Verilog, Spice, C, C#, Fortran, Cadence Skill, VBScript, Javascript, DHTML, ASP, SQL, PHP, Visual Studio, .NET., Java. Operating System Proficiency: Unix (Sun), MS-DOS, Windows/NT, Windows/XP, VAX VMS, OS/2., Linux CAD ... - 2018 Jul 16
... Software Language Proficiency: Verilog, Spice, C, C#, Fortran, Cadence Skill, VBScript, Javascript, DHTML, ASP, SQL, PHP, Visual Studio, .NET., Java. Operating System Proficiency: Unix (Sun), MS-DOS, Windows/NT, Windows/XP, VAX VMS, OS/2., Linux CAD ... - 2018 Jul 16