NITIN MISTRY

714-***-****

aczjeb@r.postjobfree.com

OBJECTIVE

To obtain a challenging permanent position as an FPGA Design Engineer where my experience and educational training will provide valuable contributions to a company’s objectives.

Summary Of Experience

FPGA and ASIC Design

Aerospace/Defense

Image Processing

Printing Technology

Board Level Design

VHDL & Verilog

EDA Tools

Xilinx Vivado, ISE, CoreGen, and ChipScope Pro Tools

Altera Quartus

Actel/Microsemi Libero Software

ModelSim

Actel Design Software

Aldec Active-HDL

Synopsys

Cadence BuildGates

Cadence NC-VHDL

Orcad

DxDesigner

EXPERIENCE

SENIOR ENGINEER (May 2016 - present)

Jet Propulsion Laboratory

Contract Position

Pasadena, CA

Designed Xilinx Kintex-7 FPGA with interface to SDRAM and NAND Flash memories for imaging system for Mars Rover 2020. Interfaced to DDR3 memory utilizing Xilinx IP generator for Xilinx Artix-7 FPGA. Utilized Xilinx Vivado Suite and Modelsim.

SENIOR ENGINEER (2013 – 2014)

Moog Aircraft

Contract Position

Torrance, CA

Designed Actel(Microsemi) FPGAs for Flight Control Computer systems. Interfaced with various processors, controllers, ADCs and DACs.Developed testbenches and performed simulations with Modelsim. Utilized Microsemi Libero software. Utilized Identify Embedded Logic Analyzer Software.

Involved in the debug of analog and digital Freescale processor based hardware.

SENIOR ENGINEER (2010 - 2013)

Parker Aerospace

Contract Position

Irvine, CA

Designed Xilinx and Lattice FPGAs for flight control system modules. FPGAs interface to microcontrollers, ADCs, DACs and various communication interfaces. Developed testbenches and performed simulations with Modelsim. Utilized Xilinx ISE tools, CoreGen, Chipscope Pro and Lattice Diamond software.

Designed a Freescale MPC5566 32-bit microcontroller based mixed-signal board with FPGA's, Analog to Digital Converters (ADC), and power supplies for flight control systems. Guided layout engineers to place and route board. Debugged board and developed manufacture for test platform and manufacturing test procedure.

SENIOR ENGINEER (2006-2010)

L-3 Communications

Anaheim, CA

Designed Xilinx and Actel FPGAs in VHDL for data communications and closed-loop control systems for power conversion systems.

FPGA modules designed include:

Customizing Xilinx PCI Core and designing PCI User Backend Interface

Data Recovery Module

Infinite Impulse Response (IIR)Filter

8B/10B Encoder/Decoder Modules

DSP and A/D Converter Interface

UART

Modbus Interface

Developed testbenches, simulations with ModelSim, and FPGA synthesis and place and route with Xilinx ISE or Actel Design Tools. Utilized Xilinx CoreGen to develop cores and Xilinx ChipScope Pro for debugging.

Wrote company VHDL Coding Standard.

SENIOR ENGINEER (2005-2006)

OleumTech

Irvine, CA

Designed RF Controller Board utilizing TI MSP430 mixed-signal processor and Xemics 1203 RF transceiver. Schematic capture with Orcad. Used spectrum analyzer.

SENIOR ASIC ENGINEER (2000 - 2003)

Printronix Corp.

Irvine, CA

Codesigner and Responsible Engineer for Printer Controller ASIC (.35 micron, 66 Mhz) for various families of printers (Laser and Impact). The ASIC consisted of:

PCI interface

DMA controller

Interrupt Controller

Specialized Printer Function Modules

Host communications Modules

RTL coding and test bench development done in VHDL. Performed functional and gate-level simulations with Cadence NC-VHDL simulator. Utilized Cadence BuildGates for synthesis and performed static timing analysis. Closely interfaced with ASIC vendor (AMI Semiconductor) application and layout engineers during ASIC design cycle. Attended Ambit training course (2 day).

Supported the conversion of three ASICs from Mitel to AMI foundry. Performed gate-level simulation of the ASICs to verify functionality and timing constraints were met. Interfaced with ASIC vendor (AMIS) application engineers.

SENIOR ASIC ENGINEER (1996 - 1999)

Conexant Systems

Newport Beach, CA

Codesigned an ASIC (.35 micron, 48 Mhz) for Digital Video Camera applications. ASIC receives pixel data from CMOS imager and performs:

RGB to YcrCb conversion

Image Scaling

Compression

Histogramming

Frame Buffering (internal or external RAM)

USB Interface

Designed several large blocks and testbenches of the ASIC in Verilog. Performed functional and gate-level simulation using Modelsim. Developed testbenches in Verilog. Utilized Synopsys for synthesis. Attended Synopsys training course in ASIC design (5 day).

Designed Universal Serial Bus (USB) Interface for Multifunctional

Peripheral Controller (.35 micron, 48 MHz) ASIC used for FAX,

scanning and printing applications. Performed functional and gate- level simulation using ModelSim. Developed test benches in Verilog.

Utilized Synopsys for synthesis.

HARDWARE DESIGN ENGINEER (1994 - 1996)

AT&T Microelectronics

Huntington Beach, CA

Involved with the design, development and test of

data/fax/voice modems using the AT&T high speed modem chip

set. Logic analyzers, telephone network emulators (TAS) and

oscilloscopes are utilized for testing and troubleshooting.

ASIC DESIGN ENGINEER (1992 - 1994)

Interstate Electronics Corporation

Anaheim, CA

Involved with the design of a high speed 90,000 gate GaAs ASIC

used in satellite communications system. Responsibilities

included functional and at-speed simulation with Cadence

RapidSim simulator and also functional and at-speed

simulations with LASAR (LASAR is Vitesse's golden simulator).

Also redesigned portions of the ASIC to meet timing and

funtional constraints. ASIC schematic capture was done with

Cadence Concept. Also utilized Motive for static timing

analysis.

HARDWARE DESIGN ENGINEER (1991 - 1992)

Matsushita Avionics Development Corporation

Irvine, CA

Designed and tested a Motorola 68000 microprocessor based

data communications unit for airline passenger audio/video

entertainment system. Serial communication controllers (Z85230)

control RS-485 data links and communicate with the

68000 via shared RAM. DMA controllers (Intel 8237) transfer

data between the Z85230s and shared RAM. 68000 access to

shared RAM, Z85230s and DMA controllers is controlled by local

bus arbitration logic. Designed PALs and GALs for various

hardware functions including state machines. Had a vital

role in system integration. Wrote software tests in C and

68000 Assembly.

HARDWARE DESIGN ENGINEER (1989 - 1991)

Librascope Corporation

Glendale, CA

Involved in the development of an advanced graphics system.

Completed the design of a 2 MB dual-ported VMEbus DRAM board.

Wrote software tests in C, 68020 Assembly, and graphics

microcode.

EDUCATION

M.S. IN ELECTRICAL ENGINEERING (1988)

University of Southern California

B.S. IN ELECTRICAL ENGINEERING (1986)

University of Southern California

ACADEMIC

COURSES

VLSI Design, Microprocessor based Design, Digital and Analog

Design, Logic Design and Switching Theory, Computer System

Architecture, Data Networks, and Software Design

CITIZENSHIP

United States

SECURITY CLEARANCE

I have had security clearances in the past.

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