| Resume alert | Resumes 61 - 70 of 424 |
Design Engineer Engineering
San Jose, CA, 95125
... These included: Multiple IP (ARM7, ARM9/ 11 Cortex, SPARC, DSP, Analog mixed signal IP cores) integration, benchmarking and SoC designs NPS Femto Satellite redesign Undersea LiDaR research and development Synthesis and Scan design regression, TRW, ... - 2019 Apr 28
... These included: Multiple IP (ARM7, ARM9/ 11 Cortex, SPARC, DSP, Analog mixed signal IP cores) integration, benchmarking and SoC designs NPS Femto Satellite redesign Undersea LiDaR research and development Synthesis and Scan design regression, TRW, ... - 2019 Apr 28
Electrical Engineering Design
San Jose, CA
... Performed logic synthesis and generated vector file consisted of data input and scan chain trace verification (DFT), applied gate level simulation and Timing Closure. Deployed Static Voltage Frequency Scaling (SVFS) to accomplish low power design. 8 ... - 2019 Apr 05
... Performed logic synthesis and generated vector file consisted of data input and scan chain trace verification (DFT), applied gate level simulation and Timing Closure. Deployed Static Voltage Frequency Scaling (SVFS) to accomplish low power design. 8 ... - 2019 Apr 05
Engineer Office
Mountain View, CA
... Achievements at the previous job: He developed a technology of mechano-activation synthesis for producing low-temperature thermoelectric triple alloys based on bismuth telluride and a switching alloy of nickel antimonide, developed an isolated argon ... - 2019 Mar 18
... Achievements at the previous job: He developed a technology of mechano-activation synthesis for producing low-temperature thermoelectric triple alloys based on bismuth telluride and a switching alloy of nickel antimonide, developed an isolated argon ... - 2019 Mar 18
Project Research
Milpitas, CA
... Lipids are a group of molecules that include fats and waxes, and they generally preserve better in sediments over long periods of time than molecules like DNA and protein SKILL SETS Chemistry Skills: Strong Peptide and Organic synthesis skills, air ... - 2019 Jan 06
... Lipids are a group of molecules that include fats and waxes, and they generally preserve better in sediments over long periods of time than molecules like DNA and protein SKILL SETS Chemistry Skills: Strong Peptide and Organic synthesis skills, air ... - 2019 Jan 06
Assistant Administrative
San Jose, CA
... CHOWDHURY (C) 408-***-**** ac7ore@r.postjobfree.com www.linkedin.com/in/chowdhuryfahima San Jose, CA QUALIFICATION SUMMARY Experienced in characterization, design, Gate-level simulation, synthesis and debugging RTL Design (Verilog) Hardware ... - 2018 Nov 13
... CHOWDHURY (C) 408-***-**** ac7ore@r.postjobfree.com www.linkedin.com/in/chowdhuryfahima San Jose, CA QUALIFICATION SUMMARY Experienced in characterization, design, Gate-level simulation, synthesis and debugging RTL Design (Verilog) Hardware ... - 2018 Nov 13
Engineer Design
San Carlos, CA
... KEY ACHIEVEMENTS GPU integration: Fullchip hierarchical synthesis flow development/deployment/support; hierarchical equivalence checking; Spyglass LINT/PT Constraint Consistency Checking flow development/deployment/support. Leading technology nodes ... - 2018 Nov 11
... KEY ACHIEVEMENTS GPU integration: Fullchip hierarchical synthesis flow development/deployment/support; hierarchical equivalence checking; Spyglass LINT/PT Constraint Consistency Checking flow development/deployment/support. Leading technology nodes ... - 2018 Nov 11
Design and Verification Engineer
San Jose, CA
... • Skills: Code/ Functional Coverage Analysis, Assertions (SVA), Constrained Random Test, UVM Components, TLM and OOP concepts, Functional and Formal Verification, RTL Design, Digital Logic Design, Synthesis, Timing analysis (STA), Protocols (AXI, ... - 2018 Oct 29
... • Skills: Code/ Functional Coverage Analysis, Assertions (SVA), Constrained Random Test, UVM Components, TLM and OOP concepts, Functional and Formal Verification, RTL Design, Digital Logic Design, Synthesis, Timing analysis (STA), Protocols (AXI, ... - 2018 Oct 29
Engineer Electrical Engineering
San Jose, CA
... of California, Davis Blood Cell Imager for Smartphones, Digital IC Design Project January 2011 – June 2012 ● Verilog, synthesis, place and route, ASIC design, Cadence Encounter, ADC, controller, filter, SRAM, I2C, low-power methodology, product ... - 2018 Oct 25
... of California, Davis Blood Cell Imager for Smartphones, Digital IC Design Project January 2011 – June 2012 ● Verilog, synthesis, place and route, ASIC design, Cadence Encounter, ADC, controller, filter, SRAM, I2C, low-power methodology, product ... - 2018 Oct 25
Test Cases
Fremont, CA
... Support, co-ordination and responsibility of the testing activities which includes review of test cases and test conditions, walkthrough the test cases / Test scenarios with clients Transaction Synthesis Layer (TSL) Description: TSL is to enable ... - 2018 Oct 24
... Support, co-ordination and responsibility of the testing activities which includes review of test cases and test conditions, walkthrough the test cases / Test scenarios with clients Transaction Synthesis Layer (TSL) Description: TSL is to enable ... - 2018 Oct 24
Mechanical Engineer
San Jose, CA
... Analyzed the competitive analysis done by students on risk and reliability of the components ACADEMIC PROJECTS Kinematic Analysis & Synthesis of an Extended 6 bar labeling mechanism Duration: 4 months Performed kinematic analysis of the output link ... - 2018 Oct 01
... Analyzed the competitive analysis done by students on risk and reliability of the components ACADEMIC PROJECTS Kinematic Analysis & Synthesis of an Extended 6 bar labeling mechanism Duration: 4 months Performed kinematic analysis of the output link ... - 2018 Oct 01