https://www.linkedin.com/in/mitmorabia/ https://github.com/mitvmorabia SUMMARY: Experienced Masters Graduate specialized in Design and Verification of ASICs/FPGAs/SOCs and hands-on with Machine Learning with 3+ years as Application Engineer and 8 months as FPGA & Machine Learning intern. TECHNICAL SKILLS
• Programming Languages: Verilog HDL, System Verilog (SV), UVM, Python, TCL, Perl.
• EDA Tools: Synopsys VCS, Design Compiler, Xilinx Vivado, Altera Quartus, ModelSim.
• Skills: Code/ Functional Coverage Analysis, Assertions (SVA), Constrained Random Test, UVM Components, TLM and OOP concepts, Functional and Formal Verification, RTL Design, Digital Logic Design, Synthesis, Timing analysis (STA), Protocols (AXI, AHB, APB, I2C, UART), Debugging and Testing, Scripting, Version Control - Git. WORK EXPERIENCE
ASIC Design Independent Contractor, SSR Labs, Santa Clara Jul. 2018 – Sep. 2018
• Design and verification of Asynchronous FIFO and switching unit for Ethernet Data Link layer for MAC.
• Assisted in design of specification at micro-architecture level for 10GBe MAC Data Link and interface layer and created python script to generate RTL code for LDPC Encoder and de-mapper algorithm for PHY layer.
• Skills and Technologies: Verilog, System Verilog, Xilinx Vivado, Python. FPGA and Machine Learning Intern, Aromatix Inc, Santa Clara Sep. 2017 – May 2018
• Designed prototype and verified RTL design (ADC, Frequency Counter and UART Transmission) using ALTERA Cyclone V FPGA. Debugging of FPGA output ADC bits using Python script, oscilloscope and function generators.
• Developed automated test scripts and parsers using Python for data pre-processing, data exploration, feature extraction, n-fold cross validation. Built and trained Support Vector Machine (SVM) for an accuracy of 83.7%.
• Skills and Technologies: Verilog, Python (Numpy, Scikit-Learn, Matplotlib, pandas), Tensorflow, GitHub. Applications Engineer, Motwane Pvt. Ltd., Mumbai Apr. 2013 – Jul. 2016
• Provided committed technical engineering support, product development, PCB design (schematic, layout) and marketing support. Served as an interface between R&D team and sales & marketing team and key customers.
• 2 years of experience in python programming, debugging and analysis of complex customer issues, creating datasheets and lab reports, documentation review, creating and reviewing functional specifications.
• Skills: Pre/Post-Sales, Technical Support, Problem Solving, Team player, Communication Skills. PROJECTS (Available on Github)
Verification IP for communication systems (UVM, Python, System Verilog, Machine Learning) Feb. 2018 – May 2018
• Using Costas loop as a DUT and developing a Machine Learning Verification IP (SVM Classifier) for UVM environment with components like sequencer, driver, monitors, scoreboards for jitter analysis. LCD Controller (UVM, System Verilog, Python, TCL, AHB Bus) Aug. 2017 – Dec. 2017
• Verification of LCD controller by implementing the complete UVM test bench (monitors, checkers, scoreboard).
• 4 DUTS where verified with AHB interface and Bus Functional Model to interact with the DUT. 64-bit signed ALU CPU Booths Algorithm (Verilog, ModelSim, Synopsys VCS, NC Verilog) Sep. 2016 – Dec. 2016
• RTL design, Pre-synthesis and post-synthesis simulation, Setup & Hold Time violation, Place and Route (P&R); performance analysis of a CPU with clock cycles, total timing, area and power constraints. Interfacing bridge between I2C and APB (Verilog, I2C, APB, ModelSim) Jul. 2018 – Aug. 2018 Design of DDR3 Memory Controller (System Verilog, Synopsys VCS, SOC, Linux, Perl) Sep. 2017 – Dec. 2017 Design of 32-bit IFFT (Verilog, Python, Synopsys VCS, Floor Plan, Partitioning, ASICs) Jan. 2017 – May 2017 EDUCATION
Masters (MS), Electrical Engineering (Digital VLSI), San Jose State University, GPA 3.3 May 2018 Coursework: Digital System Design and Synthesis, ASIC CMOS Design, Advance Computer Architectures, Semiconductor Devices, SOC Design (System Verilog), System Verification (UVM), Machine Learning