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Engineer Design

San Carlos, CA
November 11, 2018

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Kuang-Te Lee

650-***-**** (C) email:

OBJECTIVE Work with world class team to build successful semiconductor products/service. KEY ACHIEVEMENTS

GPU integration: Fullchip hierarchical synthesis flow development/deployment/support; hierarchical equivalence checking; Spyglass LINT/PT Constraint Consistency Checking flow development/deployment/support.

Leading technology nodes performance verification methodology/extraction/flow deployment and support. PT-OCV/DMSA/ECO/PTPX/STARRC.

Lead timing integration effort and CAD flow development for Ultra-SPARC III toward first tapeout.

Timing verification: develop/execute/improve timing flow and debugging timing issues for supporting Micron Flash designs (mixed A/D).

Logic Synthesis Flow improvement; CDC and constraint checking for ASIC designs; Formal Verification.

Verification speedup over 50% for an uP project through optimization of tool usage.

Lead methodology development in STA, design implementation with Physical Synthesis.

Designed and developed several modeling techniques for improving synthesis QoR including NLDM at Synopsys.


EDA: Deeply involved in the SoC design flow. Expert level of knowledge about various aspects of the EDA tools including logic/physical synthesis (Design Compiler Topographical/DCG/RTL Compiler/Physical Compiler), timing analysis (PrimeTime/PrimeTime-SI/OCV/PT-PX), Cross Clock Domain Checks (Atrenta SpyGlass/Cadence), ICCII, library modeling/characterization

(NanoTime/Library Technology/ SiliconSmart), verification (VCS/NCVerilog/Verdi), equivalence checking (Formality), UPF and DFT.

Programming: Years of industrial software/flow development experience (Python, Makefile, Perl, TCL, SystemVerilog, Perforce, C).


Oct 2015 – Present Samsung Semiconductor, San Jose Senior Staff Engineer

Key Achievements:

Synthesis fullchip integration and flow development

Synthesis QoR improvement (DCG)/new flow development/ICCII interface integration/PPA improvement

PTPX/PrimeRail/PT/PT-GCA/Spyglass Lint

Formality flow development/verification (hierarchical) and RTL2RTL

Technology node migration (14/10/8nm)

2014 – Oct 2015 Intel Corporation.

Performance Verification Lead, Intel Custom Foundry Key Achievements:

ICC-PT correlation to achieve timing closure in pre-sale PPA

Leading technology nodes performance verification methodology/flow deployment and integration

Pre-sale PVT customer interaction; PV margin discussion; PV training; PPA

POCV/AOCV/MIS/PT-ECO (physical Aware/power/timing/DMSA)/ HyperScale/Tempus/STARRC/QRC/MCMM/Low Power

Post-sale support/PV Audit

2005 - 2014 Micron Technology, Inc.

Timing Verification Manager

Methodology development:

Multi-voltage domains STA methodology development with PTSI/UPF

STA ECO methodology for timing closure and area/leakage optimization (TCL scripts)

Multi-corners STA timing closure

Glitch detection in asynchronous set/reset

Key Achievements:

Developing fullchip STA constraint for multi-voltage/multi-clock semi-customer design.

Developed fullchip STA methodology using PrimeTime/STAR-RC for Flash Memory Design (mixed A/D semi-custom design)

Developed constraint and cross clock domain checking (CDC) methodology for ASIC design with customized .synchronizers/handshaking synchronization/FIFO synchronization protocol. CDC for asynchronous glitch checks.

Macro characterization using NanoTime.

Tapeout multiple Flash designs. Responsible for STA using PrimeTime/SI for the controller; netlist generation from DFII and parasitic extraction using STARRC. Guided designers to adopt digital flow; create timing constraint; develop better synthesis methodology (DC-TOPO) ; resolve synthesis/STA issues; enhance library quality to achieve better synthesis QoR, and create formal flow using Formality to perform equivalency checking/Spyglass flow for RTL linting.

Improved standard cell cell/macro characterization methodology


1998- 2005 Sun Microsystems

Project Lead/Staff Engineer


Lead several timing integration efforts and STA methodology development for Ultra-SPARC III/ V and test chip.

Lead Physical Compiler evaluation project, with EDA/ASIC vendor, and deployed to several ASIC/uP design projects.

Lead RTL Compiler evaluation project, with EDA/ASIC vendor, from logic synthesis to P&R.

Worked with design team and ASIC vendor on functional/DFT/block level/fullchip constraint, for a multiple-millions gate networking ASIC chip with PrimeTime (20+ clock domains).

Developed methodology to enable physical synthesis (Physical compiler) with merged constraints and deployed to ASIC projects.

Developed timing false path identification methodology using PrimeTime and ATPG tool.

Supported NanoEncounter and its best practice methodology for various design projects.

Lead evaluation of multiple PCI-Express implementations IPs.

Lead evaluation and deployment of the MDC (Millennium Delay Calculator) product to improve the overall accuracy for STA.


Lead a team to develop timing/implementation CAD flow for Ultra-SPARC procsssors.

Delivered tapeout 1.0 and several intermediate integrations timing for Ultra-SPARC III.

Took full responsibility of figuring out the integration timing flow (with no support due to unforeseen circumstance) and enhanced the flow to improve the turnaround time by 50% (from 2 days to 1 day).

Lead integration effort for an ASIC project with Design Compiler.

Speedup the verification suite over 50% for an uP project. 1996 – 1998 Synopsys, Inc.

Senior QoR CAE

Lead a team of CAE to work with R&D and field to perform DC benchmark for a customer. Reduced the runtime and worst/total slack time significantly after applying the newly developed techniques.

Established automated benchmark suite for Design Compiler for facilitating QoR measurement during each phase of testing.

Provide technical support to the field and support center on issues for Design Compiler family products.

1992 – 1996 Synopsys, Inc.

Senior R&D Engineer

Designed and developed synthesis and simulation modeling solutions for the Library Compiler product including the nonlinear delay model (NLDM) for PrimeTime/Design compiler, dynamic power modeling, physical resources modeling (LEF), etc. Responsible for library format design and software development.

Provided support for customer benchmark: converted customer and competitor internal data into Synopsys technology libraries; generated timing report from the Design Compiler using the nonlinear delay model and verified the accuracy against ASIC vendors’ internal delay model to convince them to migrate to nonlinear delay model.

Responsible for problem tracking, bug fixes and quality management of the Library Compiler product, which becomes Synopsys’ best quality tool?

Achieved several internal release milestones on time for all the synthesis products. Performed the build, regression run and management of code changes to ensure the product release quality and schedule.

Prior Experience:

Improved the performance of the customer equation evaluation functionality of the Timing Preprocessor product and enhanced the product with new functionalities.

Enhanced and validated an automatic chip delay test pattern generation program

Designed and developed an interactive timing analysis application for synchronous multiple clock phases gate array design and added hierarchical functionality by creating timing model generation package.


MSEE, Rensselaer Polytechnic Institute, Troy, New York BSEE, National Chiao-Tung University, Hsinchu, Taiwan

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