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Engineer Electrical Engineering

San Jose, CA
October 25, 2018

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Oleg Loskutoff

**** ****** **., *** ****, CA ****1



Software – Python, shell scripting, PyCharm, Git, C, GNU x86 assembly, Visual Studio EDA Tools – Veloce, TBX, Cadence, Quartus, SPICE, ModelSim, Synopsis, Matlab, Verilog HDL Graphics APIs testing – DirectX 9, DX10, DX11, DX12, OpenGL, OpenCL. OS and Others – Windows 7-10, Server 2012/2016, Linux, Chromium, RedHat, Excel, PowerPoint. WORK EXPERIENCE

Validation Associate UST Global at Intel Corp., Santa Clara, CA ChromeOS Product Engineering Validation Team, SSG April 2018 – October 2018

● Chromebook validation, JIRA, Coreboot and EC log monitoring, functional testing

● Firmware flashing, servo board, HP ALM/QC, ChromeOS SDK, Fabric, Autotest Accomplishments:

● Contributor to dependency requirements for internal automation API installation guide.

● Preparing, monitoring, and reporting of stability tests running across 15+ DUTs. Validation Technician III Kelly OCG at Intel Corp., Folsom, CA Post-Si SSD PCIe NVMe Compatibility Validation Team, NSG February 2016 – September 2017

● Bash, batch, Confluence, triage, U.2, M.2, AIC, firmware loading, Medusa tests, BIOS updating, RAID testing, root cause analysis assistance, EFI, UART

● Development, scrum, automation, JIRA, Python, test tools, git repo, Altiris test execution Accomplishments:

● Python command line logging function within a private member in the main abstract class test file.

● Developed method for RAID rebuilding if testing within certain Linux flavors.

● Created a reduced version of the Basic Acceptance Test using factor scaling. Test Technician I Kelly OCG at Intel Corp., Folsom, CA Pre-Si Graphics Software Validation Team, VPG February 2013 – January 2016

● Python, batch, C, xen, virtual machine OS prep, driver debug testing, driver installs

● Veloce emulation, build simulation, Direct3D, OpenCL, OpenGL, and benchmark frames testing Accomplishments:

● Coded input script in Python for internal database API which helped issue hundreds of tasks through a nested loop through two variables, driver and simulation build, that cut down execution time immensely.

● Created text parser in C for quickly reporting both full and partial test execution results. Engineering Research Assistant California State University Sacramento Activity Monitoring for Biomedical Applications June 2007 – August 2009

● Testing, validation, oscilloscope, multimeter, monitoring environment setup

● Diodes, transistors, soldering equipment, daily documentation of lab work, weekly reporting Accomplishments:

Analyzed and recorded waveform output from recent activity monitoring sessions for providing good data points to professor/supervisor.


University of California, Davis

B.S. Electrical Engineering, 2012

Coursework: Verilog, ASIC design, verification, testing through Cadence EDA tool Heald College

Certificate, Computer Business Administration, 1999 UNIVERSITY PROJECTS

Digital IC Design Team Member University of California, Davis Blood Cell Imager for Smartphones, Digital IC Design Project January 2011 – June 2012

● Verilog, synthesis, place and route, ASIC design, Cadence Encounter, ADC, controller, filter, SRAM, I2C, low-power methodology, product and marketing strategy

● SimVision, ModelSim, Compression module development in Verilog for best performance with low overhead

Digital Systems Team Member University of California, Davis Multi-bit ALU for Image DSP Chip, VLSI Design Project September 2010 – December 2010

● Research, design, simulation, multi-block arithmetic logic, power and timing performance criteria

● Clock tree design, chip-packaging, Verilog, ModelSim, computer architecture

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